IOS LLE: execute ARMv5TE enhanced DSP instructions (StarletOS phase 11 I1)
SMLAxy, SMLAWy, SMULWy, SMLALxy, SMULxy, QADD, QSUB, QDADD and QDSUB were decoded as compare data processing that writes no register; the ARM926EJ-S implements them. The interpreter now executes them with the Q flag and the JIT leaves them to it. Adds ARMv5TEEnhancedDSPInstructions. Co-Authored-By: Claude Opus 5.5 <[email protected]>
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@@ -1423,6 +1423,16 @@ void ARMCore::ExecuteARM(u32 instruction)
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return;
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}
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// ARMv5TE enhanced DSP instructions (ARM Architecture Reference Manual, ARMv5TE): SMLAxy,
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// SMLAWy, SMULWy, SMLALxy, SMULxy, then QADD, QSUB, QDADD, QDSUB. They sit in the
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// data-processing space with a compare opcode and S clear, which ARMv5 reserves for such
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// miscellaneous instructions; decoded as data processing they would write no register.
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if ((instruction & 0x0f900090) == 0x01000080 || (instruction & 0x0f900ff0) == 0x01000050)
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{
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ExecuteEnhancedDSP(instruction);
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return;
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}
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if ((instruction & 0x0f8000f0) == 0x00800090)
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{
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ExecuteMultiplyLong(instruction);
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@@ -2327,6 +2337,87 @@ void ARMCore::ExecuteMultiply(u32 instruction)
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SetNZ(result);
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}
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void ARMCore::ExecuteEnhancedDSP(u32 instruction)
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{
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// StarletOS phase 11 (I1). The ARM926EJ-S implements these; the Q flag (CPSR bit 27) is sticky
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// and set on signed overflow of an accumulation or on saturation.
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const auto half = [](u32 value, bool top) {
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return static_cast<s64>(static_cast<s16>(top ? value >> 16 : value));
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};
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const auto saturate = [this](s64 value) {
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if (value > std::numeric_limits<s32>::max())
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{
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m_cpsr |= CPSR_Q;
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return static_cast<u32>(std::numeric_limits<s32>::max());
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}
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if (value < std::numeric_limits<s32>::min())
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{
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m_cpsr |= CPSR_Q;
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return static_cast<u32>(std::numeric_limits<s32>::min());
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}
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return static_cast<u32>(static_cast<s32>(value));
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};
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const auto accumulate = [this](s64 sum) {
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if (sum != static_cast<s32>(sum))
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m_cpsr |= CPSR_Q;
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return static_cast<u32>(static_cast<s32>(sum));
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};
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const u32 op = (instruction >> 21) & 3;
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const u32 rm = instruction & 0xf;
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if ((instruction & 0xf0) == 0x50)
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{
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// QADD (0), QSUB (1), QDADD (2), QDSUB (3): Rd = sat(Rm +/- [sat(2 *)] Rn).
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const u32 rn = (instruction >> 16) & 0xf;
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const u32 rd = (instruction >> 12) & 0xf;
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const s64 m = static_cast<s32>(ReadRegisterOperand(rm));
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s64 n = static_cast<s32>(ReadRegisterOperand(rn));
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if ((op & 2) != 0)
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n = static_cast<s32>(saturate(2 * n));
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m_registers[rd] = saturate((op & 1) != 0 ? m - n : m + n);
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return;
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}
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// SMLAxy (0), SMLAWy/SMULWy (1), SMLALxy (2), SMULxy (3). Rd (RdHi) is bits 19-16, Rn (RdLo)
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// bits 15-12, Rs bits 11-8; x (bit 5) picks Rm's half, y (bit 6) Rs's half.
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const u32 rd = (instruction >> 16) & 0xf;
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const u32 rn = (instruction >> 12) & 0xf;
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const u32 rs = (instruction >> 8) & 0xf;
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const bool x = (instruction & (1U << 5)) != 0;
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const bool y = (instruction & (1U << 6)) != 0;
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const u32 m = ReadRegisterOperand(rm);
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const u32 s = ReadRegisterOperand(rs);
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switch (op)
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{
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case 0:
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m_registers[rd] =
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accumulate(half(m, x) * half(s, y) + static_cast<s32>(ReadRegisterOperand(rn)));
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break;
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case 1:
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{
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// The top 32 bits of the 48-bit product of Rm and a halfword of Rs.
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const s64 product = (static_cast<s64>(static_cast<s32>(m)) * half(s, y)) >> 16;
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if (x) // SMULWy
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m_registers[rd] = static_cast<u32>(static_cast<s32>(product));
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else // SMLAWy
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m_registers[rd] = accumulate(product + static_cast<s32>(ReadRegisterOperand(rn)));
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break;
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}
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case 2:
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{
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const u64 accumulator =
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(static_cast<u64>(ReadRegisterOperand(rd)) << 32) | ReadRegisterOperand(rn);
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const u64 result = accumulator + static_cast<u64>(half(m, x) * half(s, y));
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m_registers[rn] = static_cast<u32>(result);
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m_registers[rd] = static_cast<u32>(result >> 32);
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break;
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}
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default:
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m_registers[rd] = static_cast<u32>(static_cast<s32>(half(m, x) * half(s, y)));
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break;
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}
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}
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void ARMCore::ExecuteMultiplyLong(u32 instruction)
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{
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const bool signed_multiply = (instruction & (1U << 22)) != 0;
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@@ -315,6 +315,8 @@ private:
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void TraceWatchedBlockTransfer(u32 address, u32 size, bool load) const;
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void ExecuteMultiply(u32 instruction);
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void ExecuteMultiplyLong(u32 instruction);
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// ARMv5TE signed halfword multiplies and saturating arithmetic.
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void ExecuteEnhancedDSP(u32 instruction);
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void ExecuteBranch(u32 instruction);
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void ExecuteCoprocessor(u32 instruction);
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void ExecutePSRTransfer(u32 instruction);
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@@ -1164,7 +1164,9 @@ bool ARMJitX64::CanEmitARMDataProcessing(u32 instruction) const
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if ((instruction & 0x0fff0ff0) == 0x016f0f10 || (instruction & 0x0f8000f0) == 0x00800090 ||
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(instruction & 0x0fc000f0) == 0x00000090 || (instruction & 0x0fb00ff0) == 0x01000090 ||
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(instruction & 0x0fbf0fff) == 0x010f0000 || (instruction & 0x0fb0fff0) == 0x0120f000 ||
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(instruction & 0x0fb0f000) == 0x0320f000 || (instruction & 0x0e000090) == 0x00000090)
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(instruction & 0x0fb0f000) == 0x0320f000 || (instruction & 0x0e000090) == 0x00000090 ||
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// ARMv5TE enhanced DSP multiplies and saturating arithmetic: interpreter (StarletOS I1).
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(instruction & 0x0f900090) == 0x01000080 || (instruction & 0x0f900ff0) == 0x01000050)
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{
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return false;
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}
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@@ -1755,6 +1755,83 @@ TEST(StarletARMCore, ARMJitCompilesLongMultiplyFamily)
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#endif
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}
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TEST(StarletARMCore, ARMv5TEEnhancedDSPInstructions)
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{
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// StarletOS phase 11 (I1): encodings from GNU as (-march=armv5te); results from the ARM
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// Architecture Reference Manual. r0 = Rm, r1 = Rs or Rn, r7 = accumulator, r3/r4 results.
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struct Case
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{
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u32 instruction;
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u32 r0;
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u32 r1;
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u32 r3;
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u32 r4;
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u32 r7;
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u32 expected_r3;
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u32 expected_r4;
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bool expected_q;
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};
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constexpr std::array cases = {
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// smlabb r4, r0, r1, r7: a 88-byte entry 9 of a table (Revolution's RAM layer).
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Case{0xe1047180, 9, 88, 0, 0, 0x13780000, 0, 0x13780318, false},
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Case{0xe1640180, 0xffff0003, 0x0002fffe, 0, 0, 0, 0, 0xfffffffa, false}, // smulbb
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Case{0xe16401a0, 0xffff0003, 0x0002fffe, 0, 0, 0, 0, 2, false}, // smultb
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// smlatt r4, r0, r1, r7: 0x3fff0001 + 0x7fffffff overflows, wraps and sets Q.
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Case{0xe10471e0, 0x7fff0000, 0x7fff0000, 0, 0, 0x7fffffff, 0, 0xbfff0000, true},
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Case{0xe1247180, 0x00020000, 0x00000003, 0, 0, 10, 0, 16, false}, // smlawb
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Case{0xe12401e0, 0xfffe0000, 0x00030000, 0, 0, 0, 0, 0xfffffffa, false}, // smulwt
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// smlalbb r3, r4, r0, r1: 0x00000000_ffffffff + 1 carries into RdHi.
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Case{0xe1443180, 1, 1, 0xffffffff, 0, 0, 0, 1, false},
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Case{0xe1014050, 0x7fffffff, 1, 0, 0, 0, 0, 0x7fffffff, true}, // qadd
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Case{0xe1214050, 0x80000000, 1, 0, 0, 0, 0, 0x80000000, true}, // qsub
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Case{0xe1414050, 1, 0x40000000, 0, 0, 0, 0, 0x7fffffff, true}, // qdadd
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Case{0xe1614050, 0, 3, 0, 0, 0, 0, 0xfffffffa, false}, // qdsub
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};
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for (const Case& test : cases)
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{
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TestBus interpreter_bus;
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ARMCore interpreter(interpreter_bus);
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#if defined(_M_X86_64)
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TestBus jit_bus;
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ARMCore jit(jit_bus);
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std::array<ARMCore*, 2> cores = {&interpreter, &jit};
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jit_bus.WriteARM(0, test.instruction);
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jit_bus.WriteARM(4, 0xeafffffe); // b .
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#else
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std::array<ARMCore*, 1> cores = {&interpreter};
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#endif
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interpreter_bus.WriteARM(0, test.instruction);
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interpreter_bus.WriteARM(4, 0xeafffffe); // b .
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for (ARMCore* core : cores)
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{
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core->SetCPSR(static_cast<u32>(ARMCore::Mode::System));
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core->SetRegister(0, test.r0);
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core->SetRegister(1, test.r1);
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core->SetRegister(3, test.r3);
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core->SetRegister(4, test.r4);
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core->SetRegister(7, test.r7);
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core->SetRegister(15, 0);
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}
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#if defined(_M_X86_64)
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jit.SetJitEnabled(true);
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#endif
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for (ARMCore* core : cores)
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{
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ASSERT_EQ(core->RunCycles(2), 2u);
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EXPECT_EQ(core->GetRegister(4), test.expected_r4) << std::hex << test.instruction;
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if (test.instruction == 0xe1443180)
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EXPECT_EQ(core->GetRegister(3), test.expected_r3);
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EXPECT_EQ((core->GetCPSR() & ARMCore::CPSR_Q) != 0, test.expected_q)
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<< std::hex << test.instruction;
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// The DSP instruction must not touch the condition flags (it is not a compare).
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EXPECT_EQ(core->GetCPSR() & (ARMCore::CPSR_N | ARMCore::CPSR_Z | ARMCore::CPSR_C |
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ARMCore::CPSR_V),
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0u);
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}
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}
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}
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TEST(StarletARMCore, FCSESwitchPreservesTaggedTLBTranslations)
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{
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TestBus bus(0x10000);
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@@ -53,18 +53,18 @@
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMCore.cpp",
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"sha256": "262946f1fb95250d1aa1ca73c9bc27ef5f83511731bf84c765a41b04fe7ff70a",
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"bytes": 76503
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"sha256": "2559d69e1ec654734f788312cf5f3dca4de63e22e0880626306e8d15a4585648",
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"bytes": 80026
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMCore.h",
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"sha256": "fa80b0d697e19f0aee178be4b13097ad5466f0bbd0cb9b3e7a74876c045b731f",
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"bytes": 14647
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"sha256": "c3263bebbbdb7cd1119cc74ad328a63ad969136c1755ccf8e06e6549f23da3aa",
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"bytes": 14758
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMJitX64.cpp",
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"sha256": "30ac3e6f74edd40a76406394ed40d66a1ca5b6b9a17b9699a1534d255320108f",
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"bytes": 109425
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"sha256": "724382f4f66442d51382d3249bea68620d7417a6c7f48b0c19efa60e942a183c",
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"bytes": 109615
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMJitX64.h",
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@@ -189,6 +189,15 @@
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"Source/Core/Core/IOS/Starlet/StarletMemory.cpp",
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"Source/Core/Core/IOS/Starlet/StarletMemory.h"
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]
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},
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{
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"recordedAt": "2026-10-06",
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"purpose": "StarletOS Phase 11 proposal I1: the ARM interpreter executes the ARMv5TE enhanced DSP instructions (SMLAxy, SMLAWy, SMULWy, SMLALxy, SMULxy, QADD, QSUB, QDADD, QDSUB, Q flag), previously decoded as compare data processing that wrote no register; the JIT leaves them to the interpreter; test ARMv5TEEnhancedDSPInstructions",
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"files": [
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"Source/Core/Core/IOS/Starlet/ARMCore.cpp",
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"Source/Core/Core/IOS/Starlet/ARMCore.h",
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"Source/Core/Core/IOS/Starlet/ARMJitX64.cpp"
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]
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}
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]
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}
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@@ -212,3 +212,24 @@ the one it had just written, with no other Starlet store or device DMA seen.
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- `ARMCore.cpp` keeps its CRLF bytes. 95 Starlet tests passed. Companion
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smoke run (P11-H06D, 150 s): no DIFF, no AUDIT, 9 LDM with identical
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virtual and physical addresses.
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## ARMv5TE enhanced DSP instructions — 2026-10-06
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Companion proposal I1 (approved). The companion's Revolution kernel computes
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table addresses with `smlabb`; the ARM926EJ-S executes it, but
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`ARMCore::ExecuteARM` had no case for the ARMv5TE enhanced DSP instructions,
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so `smlabb` fell into data processing as `TST` (no destination written, flags
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changed). The kernel then read the wrong RAM-layer entry and refused a
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creation -106 ("system files corrupted" in the System Menu), in the fork only.
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- `ARMCore::ExecuteEnhancedDSP`: SMLAxy, SMLAWy, SMULWy, SMLALxy, SMULxy,
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QADD, QSUB, QDADD, QDSUB, with the sticky Q flag (ARM Architecture
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Reference Manual semantics), decoded before the generic decoders.
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- `CanEmitARMDataProcessing` excludes these encodings, so the JIT leaves them
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to the interpreter.
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- Test `StarletARMCore.ARMv5TEEnhancedDSPInstructions`: eleven encodings from
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GNU as (`-march=armv5te`), interpreter and JIT, results, Q and NZCV
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untouched. 96 selected Starlet tests passed.
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- The companion's images use, besides these (16 `smlabb`, 4 `smulbb`), only
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`blx`, `clz`, `ldrd`, `strd` among the ARMv5TE additions; those were
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already handled.
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