Reorganize carry to store flags separately instead of part of XER
Also correct behavior with regards to which bits in XER are treated as zero based on a hwtest (probably doesn't affect any real games, but might as well be correct).
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@@ -61,6 +61,12 @@ struct GC_ALIGNED64(PowerPCState)
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// This variable should be inside of the CoreTiming namespace if we wanted to be correct.
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int downcount;
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// XER, reformatted into byte fields for easier access.
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u8 xer_ca;
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u8 xer_so_ov; // format: (SO << 1) | OV
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// The Broadway CPU implements bits 16-23 of the XER register... even though it doesn't support lscbx
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u16 xer_stringctrl;
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#if _M_X86_64
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// This member exists for the purpose of an assertion in x86 JitBase.cpp
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// that its offset <= 0x100. To minimize code size on x86, we want as much
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@@ -252,35 +258,40 @@ inline u32 GetCR()
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return PowerPC::CompactCR();
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}
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// SetCarry/GetCarry may speed up soon.
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inline void SetCarry(int ca)
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{
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((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).CA = ca;
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PowerPC::ppcState.xer_ca = ca;
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}
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inline int GetCarry()
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{
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return ((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).CA;
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return PowerPC::ppcState.xer_ca;
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}
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inline UReg_XER GetXER()
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{
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return ((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]);
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u32 xer = 0;
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xer |= PowerPC::ppcState.xer_stringctrl;
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xer |= PowerPC::ppcState.xer_ca << XER_CA_SHIFT;
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xer |= PowerPC::ppcState.xer_so_ov << XER_OV_SHIFT;
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return xer;
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}
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inline void SetXER(UReg_XER new_xer)
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{
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((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]) = new_xer;
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PowerPC::ppcState.xer_stringctrl = new_xer.BYTE_COUNT + (new_xer.BYTE_CMP << 8);
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PowerPC::ppcState.xer_ca = new_xer.CA;
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PowerPC::ppcState.xer_so_ov = (new_xer.SO << 1) + new_xer.OV;
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}
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inline int GetXER_SO()
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{
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return ((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).SO;
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return PowerPC::ppcState.xer_so_ov >> 1;
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}
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inline void SetXER_SO(int value)
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{
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((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).SO = value;
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PowerPC::ppcState.xer_so_ov |= value << 1;
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}
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void UpdateFPRF(double dvalue);
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