Revert "JitCache: Support for VMEM + MSR bits"
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d7de39ebbe
commit
6834b4cb27
19 files changed
+369
-447
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@@ -20,7 +20,6 @@ void CachedInterpreter::Init()
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jo.enableBlocklink = false;
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JitBaseBlockCache::Init();
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UpdateMemoryOptions();
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code_block.m_stats = &js.st;
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code_block.m_gpa = &js.gpa;
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@@ -42,29 +41,34 @@ void CachedInterpreter::Run()
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void CachedInterpreter::SingleStep()
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{
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const u8* normalEntry = jit->GetBlockCache()->Dispatch();
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const Instruction* code = reinterpret_cast<const Instruction*>(normalEntry);
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while (true)
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int block = GetBlockNumberFromStartAddress(PC);
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if (block >= 0)
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{
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switch (code->type)
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Instruction* code = (Instruction*)GetCompiledCodeFromBlock(block);
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while (true)
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{
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case Instruction::INSTRUCTION_ABORT:
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return;
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case Instruction::INSTRUCTION_TYPE_COMMON:
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code->common_callback(UGeckoInstruction(code->data));
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code++;
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break;
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case Instruction::INSTRUCTION_TYPE_CONDITIONAL:
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bool ret = code->conditional_callback(code->data);
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code++;
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if (ret)
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switch (code->type)
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{
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case Instruction::INSTRUCTION_ABORT:
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return;
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break;
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case Instruction::INSTRUCTION_TYPE_COMMON:
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code->common_callback(UGeckoInstruction(code->data));
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code++;
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break;
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case Instruction::INSTRUCTION_TYPE_CONDITIONAL:
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bool ret = code->conditional_callback(code->data);
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code++;
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if (ret)
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return;
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break;
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}
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}
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}
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Jit(PC);
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}
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static void EndBlock(UGeckoInstruction data)
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@@ -83,30 +87,14 @@ static void WritePC(UGeckoInstruction data)
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NPC = data.hex + 4;
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}
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static void WriteBrokenBlockNPC(UGeckoInstruction data)
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{
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NPC = data.hex;
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}
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static bool CheckFPU(u32 data)
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{
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UReg_MSR& msr = (UReg_MSR&)MSR;
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if (!msr.FP)
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{
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PC = NPC = data;
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PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE;
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PowerPC::CheckExceptions();
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PowerPC::ppcState.downcount -= data;
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return true;
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}
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return false;
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}
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static bool CheckDSI(u32 data)
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{
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if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI)
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{
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PowerPC::CheckExceptions();
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PowerPC::ppcState.downcount -= data;
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return true;
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}
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return false;
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@@ -173,29 +161,22 @@ void CachedInterpreter::Jit(u32 address)
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if (!ops[i].skip)
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{
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bool check_fpu = (ops[i].opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound;
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bool endblock = (ops[i].opinfo->flags & FL_ENDBLOCK) != 0;
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bool memcheck = (ops[i].opinfo->flags & FL_LOADSTORE) && jo.memcheck;
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if (check_fpu)
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if ((ops[i].opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound)
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{
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m_code.emplace_back(WritePC, ops[i].address);
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m_code.emplace_back(CheckFPU, js.downcountAmount);
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m_code.emplace_back(CheckFPU, ops[i].address);
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js.firstFPInstructionFound = true;
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}
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if (endblock || memcheck)
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if (ops[i].opinfo->flags & FL_ENDBLOCK)
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m_code.emplace_back(WritePC, ops[i].address);
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m_code.emplace_back(GetInterpreterOp(ops[i].inst), ops[i].inst);
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if (memcheck)
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m_code.emplace_back(CheckDSI, js.downcountAmount);
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if (endblock)
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if (ops[i].opinfo->flags & FL_ENDBLOCK)
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m_code.emplace_back(EndBlock, js.downcountAmount);
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}
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}
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if (code_block.m_broken)
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{
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m_code.emplace_back(WriteBrokenBlockNPC, nextPC);
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m_code.emplace_back(WritePC, nextPC);
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m_code.emplace_back(EndBlock, js.downcountAmount);
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}
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m_code.emplace_back();
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@@ -210,5 +191,12 @@ void CachedInterpreter::ClearCache()
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{
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m_code.clear();
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JitBaseBlockCache::Clear();
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UpdateMemoryOptions();
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}
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void CachedInterpreter::WriteDestroyBlock(const u8* location, u32 address)
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{
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}
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void CachedInterpreter::WriteLinkBlock(u8* location, const JitBlock& block)
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{
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}
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