Merge branch 'master' into GLSL-master

Conflicts:
	Source/Core/VideoCommon/Src/PixelShaderGen.cpp
	Source/Plugins/Plugin_VideoDX11/Src/VertexManager.cpp
	Source/Plugins/Plugin_VideoDX9/Src/VertexManager.cpp

Source/Core/Core/Src/HW/WII_IPC.cpp

@@ -28,6 +28,7 @@
 
 #include "../IPC_HLE/WII_IPC_HLE.h"
 #include "WII_IPC.h"
+#include "CoreTiming.h"
 
 
 // This is the intercommunication between ARM and PPC. Currently only PPC actually uses it, because of the IOS HLE
@@ -104,6 +105,8 @@ static u32 arm_irq_masks;
 
 static u32 sensorbar_power; // do we need to care about this?
 
+int updateInterrupts;
+
 void DoState(PointerWrap &p)
 {
 	p.Do(ppc_msg);
@@ -130,6 +133,8 @@ void Init()
 	sensorbar_power = 0;
 
 	ppc_irq_masks |= INT_CAUSE_IPC_BROADWAY;
+
+	updateInterrupts = CoreTiming::RegisterEvent("IPCInterrupt", UpdateInterrupts);
 }
 
 void Reset()
@@ -222,10 +227,10 @@ void Write32(const u32 _Value, const u32 _Address)
 	}	
 
 	WII_IPC_HLE_Interface::Update();
-	UpdateInterrupts();
+	CoreTiming::ScheduleEvent_Threadsafe(0, updateInterrupts, 0);
 }
 
-void UpdateInterrupts()
+void UpdateInterrupts(u64 userdata, int cyclesLate)
 {
 	if ((ctrl.Y1 & ctrl.IY1) || (ctrl.Y2 & ctrl.IY2))
 	{
@@ -247,7 +252,7 @@ void GenerateAck(u32 _Address)
 	ctrl.Y2 = 1;
 	INFO_LOG(WII_IPC, "GenerateAck: %08x | %08x [R:%i A:%i E:%i]",
 		ppc_msg,_Address, ctrl.Y1, ctrl.Y2, ctrl.X1);
-	UpdateInterrupts();
+	CoreTiming::ScheduleEvent_Threadsafe(0, updateInterrupts, 0);
 }
 
 void GenerateReply(u32 _Address)

Source/Core/Core/Src/HW/WII_IPC.h

@@ -52,7 +52,7 @@ void DoState(PointerWrap &p);
 void Read32(u32& _rReturnValue, const u32 _Address);
 void Write32(const u32 _Value, const u32 _Address);
 
-void UpdateInterrupts();
+void UpdateInterrupts(u64 userdata = 0, int cyclesLate = 0);
 void GenerateAck(u32 _Address);
 void GenerateReply(u32 _Address);
 

Source/Core/Core/Src/PowerPC/JitArm32/JitAsm.cpp

@@ -72,7 +72,7 @@ void JitArmAsmRoutineManager::Generate()
 			MOVI2R(R14, (u32)jit->GetBlockCache()->GetICache());
 			// Confirmed That this loads the base iCache Location correctly 08-04-12
 
-			LDR(R12, R14, R12, true, true); // R12 contains iCache[PC & JIT_ICACHE_MASK] here
+			LDR(R12, R14, R12); // R12 contains iCache[PC & JIT_ICACHE_MASK] here
 			// R12 Confirmed this is the correct iCache Location loaded.
 			TST(R12, 0xFC); // Test  to see if it is a JIT block.
 
@@ -82,7 +82,7 @@ void JitArmAsmRoutineManager::Generate()
 			// LDR R14 right here to get CodePointers()[0] pointer.
 			REV(R12, R12); // Reversing this gives us our JITblock.
 			LSL(R12, R12, 2); // Multiply by four because address locations are u32 in size 
-			LDR(R14, R14, R12, true, true); // Load the block address in to R14 
+			LDR(R14, R14, R12); // Load the block address in to R14 
 
 			B(R14);