8 Commits
Author SHA1 Message Date
Frajo Haider fd9c970621 JitArm64/Jit64: Extend the fast lookup mmap-ed segment further to avoid needing to check the msr bits.
And in order to avoid a double dereference in the dispatcher, directly store
the normalEntry in the map.

The index to the block map becomes ((((DR<<1) | IR) << 30) | (address >> 2)).
This has been chosen since the msr bits change less often than the address,
thus we keep nearby entries together.

Also do not call the C dispatcher in case the assembly dispatcher didn't
find a block, since it wouldn't find a block either due to the 1:1 mapping,
except when falling back to the non shm segment lookup table.
2023-09-15 19:46:15 +03:00
Frajo Haider 210347ae15 Tools: fix perf-disassemble.sh.
perf now passes the proper no-show-raw-insn option instead of no-show-raw.

Keep no-show-raw as a fallback for older kernels/perf-toolings.

See also: https://github.com/torvalds/linux/commit/c5baf9089246c1356705c9ba36d767ee8ce43dd2
2023-09-04 12:29:07 +03:00
Frajo Haider 7daa19f40d JitArm64: Avoid loading compilerPC multiple times if it's already in a register. 2023-08-26 18:14:07 +03:00
Franz-Josef Haider 8bfcd2deb7 JitArm64/Jit64: Load the memory register without jumps and only when necessary. 2023-07-28 14:24:53 +03:00
Franz-Josef Haider 8943a9a369 Jit: Add missing call to InitBLROptimization for extra performance 2023-05-23 23:49:29 +03:00
Franz-Josef Haider 68aab70c75 Jit: Fix block map fallback in Arm64 case. 2023-05-23 23:20:08 +03:00
Franz-Josef Haider 859da32a6c Jit: Improve block lookup performance through a shm memory segment.
By using a shm memory segment for the fast_block_map that is sparsely
allocated (i.e. on write by the OS) instead of a statically allocated
array we can make the block lookup faster by:
* Having a bigger space available for lookup that doesn't take up
  too much memory, because the OS will only allocate the needed
  pages when written to.
* Decrease the time spent to lookup a block in the assembly dispatcher
  due to less comparisions and shorter code (for example the pc check
  has been entirely dropped since only the msrBits need to be validated).

When the JIT block cache is full the shm segment will also be released
and reallocated to avoid allocating too much memory. It will also be
reset when the instruction cache is flushed by the PPC code to avoid
having stale entries.

Also fallback to the original method in case the memory segment couldn't
be allocated.
2023-05-20 16:26:55 +03:00
Franz-Josef Haider 9cd878218c Interpreter_Tables: specify FL_IN_A for twi.
rGPR[inst.RA] is an input to twi.
2021-08-27 16:59:02 +03:00