Commit Graph
1316 Commits
Author SHA1 Message Date
degasus 85affe995e JitCache: Do not use block 0.
This ID is reserved for invalid blocks. So this block can't be invalidated.
2016-08-06 14:16:13 +02:00
degasus 814f29b25b JitCache: Implement block unlinking. 2016-08-06 11:41:39 +02:00
magumagu ba39a0b3b4 Add ISI logging to interpreter. 2016-08-06 11:41:39 +02:00
magumagu ca511640a5 Add support for DSI exceptions to CachedInterpreter.
Should be straightforward.  Maybe useful for the purpose of testing.
2016-08-06 11:41:39 +02:00
magumagu 758e6406cd JIT: fix handling of PC in dispatcher/block cache.
Specifically, don't make any assumptions about what effective addresses
are used for code, and correctly handle changes to MSR.DR/MSR.IR.

(Split off from dynamic-bat.)
2016-08-06 11:41:39 +02:00
Scott Mansell 6834b4cb27 Revert "JitCache: Support for VMEM + MSR bits" 2016-07-27 11:15:25 +12:00
degasus f9e5660106 JitCache: Implement block unlinking. 2016-07-16 09:24:10 +02:00
magumagu 0de9d94de3 Add ISI logging to interpreter. 2016-07-16 09:24:09 +02:00
magumagu 0f788e0c3d Add support for DSI exceptions to CachedInterpreter.
Should be straightforward.  Maybe useful for the purpose of testing.
2016-07-16 09:24:09 +02:00
magumagu b81d008f92 JIT: fix handling of PC in dispatcher/block cache.
Specifically, don't make any assumptions about what effective addresses
are used for code, and correctly handle changes to MSR.DR/MSR.IR.

(Split off from dynamic-bat.)
2016-07-16 09:24:05 +02:00
Scott Mansell 20449ec91f Don't forget to initalize your variables. 2016-06-30 20:27:19 +12:00
Matt Mastracci 1e08ad0d97 Add MOV optimization and MOV_sum
Replaces incarnations of the A=B+C pattern throughout the
code so we can apply optimizations consistently.
2016-06-27 15:43:52 -06:00
Matt Mastracci b1296a7825 Refactor fastmem/trampoline code.
Simplication to avoid reading back the generated instructions, allowing
us to handle all possible cases.
2016-06-27 14:58:20 -06:00
Matt Mastracci 4aa5291f54 Refactor the paired load/store code
Simplification/reduction of duplicated code. Detect other constant GQR values and inline loads (5-10% speedup) and do direct dispatch to AOT methods for stores.
2016-06-26 19:49:02 -06:00
degasus ca96302a36 PowerPC: Dedoublify CheckExternalExceptions. 2016-06-26 11:29:25 +02:00
Mat M c896645313 Merge pull request #3947 from magumagu/interpreter-cleanup
Misc cleanup in Interpreter.
2016-06-26 02:11:09 -04:00
magumagu 1c28a27ee4 Delete dead variable named bFakeVMEM.
(There's another bFakeVMEM in Memmap.h.)
2016-06-25 23:05:55 -07:00
magumagu b5ed27ffa8 Misc cleanup in Interpreter.
Mostly comment changes; also gets rid of an unnecessary call to
CheckExceptions.
2016-06-25 22:52:17 -07:00
Rohit Nirmal 84cd57f99b Fix building with PCH disabled. 2016-06-24 11:46:48 -05:00
Pierre Bourdon 5fcb4bb3ab Further fixes to the formatting change. WX sucks. 2016-06-24 12:16:10 +02:00
Pierre Bourdon 3570c7f03a Reformat all the things. Have fun with merge conflicts. 2016-06-24 10:43:46 +02:00
Pierre Bourdon 2115e8a4a6 Add annotations for code sections that need to remain manually formatted. 2016-06-24 10:41:46 +02:00
Mat M 08d45b9fea Merge pull request #3794 from EmptyChaos/frame-advance-race
Core: Add synchronization to state changes (Fix Frame Step and FIFO Player -  Issue 8718)
2016-05-22 15:19:16 -04:00
degasus c5e8238cc7 JitArm64: Fix dispatcher with MMU. 2016-05-20 08:32:16 +02:00
degasus 8e902abca3 JitArm64: Implement DSI exception.
Ok, this falls back on all memory instructions, but it's a way to start.
2016-05-20 08:32:16 +02:00
degasus 5db61b4bbb JitArm64: Fix broken block handling. 2016-05-19 19:20:44 +02:00
degasus 37e2e92e33 JitArm64: Handle ISI excepction. 2016-05-19 19:20:44 +02:00
degasus 95ebb2991f JitArm64: Check Exceptions on mtmsr. 2016-05-19 19:20:44 +02:00
degasus 782c68cf00 JitArm64: Clean up LWZ idle skipping. 2016-05-19 19:20:44 +02:00
degasus 637851fce0 JitArm64: optimize bclrx
the unconditional path is the most common, so no need to switch to far code here.
2016-05-14 00:05:55 +02:00
degasus b6f16352e4 JitArm64: Check downcount on block linking.
This skips one B() call.
2016-05-14 00:04:58 +02:00
degasus 10e716c623 JitCommon: Pass jit block instead of host pointer on linking.
So the JIT may do more fancy stuff.
2016-05-14 00:04:58 +02:00
degasus cf3c65fbd0 JitArm64: Use B() instead of BR() to jumo to ASM.
Avoid indirect jumps as good as possible. This is a noticeable speedup.
2016-05-14 00:04:58 +02:00
degasus b2be9bd7f7 JitArm64: Inline JitAsm in JitArm64.
So they share the same emitter, and so they are in the same 128MB range.
This allows us to use B() to jump to the dispatcher.

However, so we have to regenerate them on every cache clear.
2016-05-14 00:04:58 +02:00
EmptyChaos c1922783f8 Core: Threadsafety Synchronization Fixes (Frame Advance / FifoPlayer)
Fix Frame Advance and FifoPlayer pause/unpause/stop.

CPU::EnableStepping is not atomic but is called from multiple threads
which races and leaves the system in a random state; also instruction
stepping was unstable, m_StepEvent had an almost random value because
of the dual purpose it served which could cause races where CPU::Run
would SingleStep when it was supposed to be sleeping.

FifoPlayer never FinishStateMove()d which was causing it to deadlock.
Rather than partially reimplementing CPU::Run, just use CPUCoreBase
and then call CPU::Run(). More DRY and less likely to have weird bugs
specific to the player (i.e the previous freezing on pause/stop).

Refactor PowerPC::state into CPU since it manages the state of the
CPU Thread which is controlled by CPU, not PowerPC. This simplifies
the architecture somewhat and eliminates races that can be caused by
calling PowerPC state functions directly instead of using CPU's
(because they bypassed the EnableStepping lock).
2016-05-13 09:23:44 +10:00
Matthew Parlane ea82fcc24f Merge pull request #3658 from Tilka/helpers
Interpreter: simplify some helpers
2016-05-03 22:44:27 +12:00
Mathew Maidment b99b685f22 Merge pull request #3800 from phire/unexceptional-exceptions
Make exceptions consistent across all JITs/Interpreters (Fixes Pokemon Box)
2016-04-29 19:48:55 -04:00
Mathew Maidment b420abc908 Merge pull request #3769 from RisingFog/remove_framestep
Remove Unused Framestop Functions
2016-04-29 19:41:25 -04:00
Scott Mansell eb5819f88a Make exceptions consistant across all JITs/Interpeters.
They all handled it diffrently, so I've just moved it into Advance()

This fixes Pokemon Box booting in JIT/JITIL which shared a bug where
exceptions set in a scheduled event would be ignored untill the next
slice (upto 20,000 cycles).
2016-04-28 17:22:52 +12:00
Chris Burgener 3140f9b226 Change GetStatePtr() Return to const 2016-04-05 12:45:48 -04:00
Pierre Bourdon 21eb1cd158 Merge pull request #3635 from phire/lazy_comex
Implement BLR Overflow handling for Windows.
2016-03-26 01:42:54 +01:00
Scott Mansell d61baef2f6 Disable JitArm64's inline timebase implemenation, as it's incorrect.
The interpeted version is correct.
2016-03-24 05:17:10 +13:00
Scott Mansell 27beef1ff4 Store an inverted copy of lastOCfactor.
The inverse operation is more common, especially when games check the
timer rapidly. So we do the division once and store the inverted copy.
2016-03-24 05:17:10 +13:00
Scott Mansell 407f86e01a Mark global variables with g_ prefix 2016-03-24 04:32:12 +13:00
Scott Mansell 2ebbfd6f85 Adjust cycle counts so they are accurate to the jit block level
Previously GlobalTimer was only updated at the end of each slice
when CoreTiming::Advance() was called, so it could be upto 20,000
cycles off.

This was causing huge problems with games which made heavy use of
the time base register, such as OoT (virtual console) and Pokemon
puzzle.

I've also made it so event scheduling will be accurate to the jit
block level, instead of accurate to the slice.
2016-03-24 04:24:53 +13:00
Scott Mansell c5b3a2efac Implement BLR Overflow handling for Windows. 2016-03-20 00:41:28 +13:00
degasus 54a4d68c9a JitArm64: implement dcbx 2016-03-05 00:29:38 +01:00
degasus 9bf50fb93d JitArm64: Fix mulli.
mulli has no inst.OE
2016-03-04 22:51:47 +01:00
degasus 9ed465f4ac JitArm64: Implement mulhwx 2016-03-04 22:51:46 +01:00
degasus 889a0d396d JitArm64: Align farcode entry points to 16 bytes 2016-03-04 22:49:02 +01:00