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2519 Commits
Author SHA1 Message Date
CrystalGamma c991904e04 PowerPC: Add reservation monitor to save state 2021-07-21 12:14:07 +02:00
CrystalGamma d763d693e8 PowerPC: Move lwarx/stwcxd. reservation into PowerPCState 2021-07-21 12:12:19 +02:00
Shawn Hoffman 8bddd8c675 remove SetRoundMode 
we only care about SSE rounding mode, and set
that manually in SetSIMDMode
 2021-07-17 19:29:22 -07:00
Shawn Hoffman 197075293d make FPSCR.RN an enum 2021-07-17 18:55:06 -07:00
JosJuice 3af21d3d22 JitArm64: Optimize FloatCompare's CR value emitting 
Setting bit 32 is only needed in the case where EQ and GT are set
but SO and LT are not, which is not a possible outcome of a compare.
 2021-07-12 22:54:37 +02:00
JosJuice 8af5095ff4 JitArm64: Stop using hand-encoded logical immediates 2021-07-12 22:25:49 +02:00
Markus Wick 88fd9fd577 Merge pull request #9869 from JosJuice/jitarm64-constexpr-isimmlogical 
JitArm64: Encode logical immediates at compile-time where possible
 2021-07-11 12:55:48 +02:00
JosJuice f903853cf7 JitArm64: Fix ps_cmpXX 
Passing a width of 64 and registers encoded as double to
DUP resulted in an invalid instruction. The registers should
be encoded as quads in this situation.

Fixes https://bugs.dolphin-emu.org/issues/12575.
 2021-07-11 11:43:19 +02:00
JosJuice 0f3b9a8874 JitArm64: Minor mcrfs optimization 2021-07-10 20:44:22 +02:00
JosJuice 9e80db123f JitArm64: Encode logical immediates at compile-time where possible 
Manually encoding and decoding logical immediates is error-prone.
Using ORRI2R and friends lets us avoid doing the work manually,
but in exchange, there is a runtime performance penalty. It's
probably rather small, but still, it would be nice if we could
let the compiler do the work at compile-time. And that's exactly
what this commit does, so now I have no excuse for trying to
manually write logical immediates anymore.
 2021-07-10 20:43:59 +02:00
Markus Wick f6ca70d094 Merge pull request #9822 from JosJuice/jitarm64-ps-cmpxx 
JitArm64: Implement ps_cmpXX
 2021-07-10 19:20:48 +02:00
JosJuice adbf6d55da JitArm64: Implement ps_cmpXX 2021-07-10 19:08:55 +02:00
Markus Wick 4ba4d7cc7d Merge pull request #9878 from JosJuice/jitarm64-addmex 
JitArm64: Implement addmex/subfmex
 2021-07-10 10:11:20 +02:00
JosJuice fc60e62622 JitArm64: Implement addmex/subfmex 2021-07-09 16:44:33 +02:00
Admiral H. Curtiss c9e4489e17 Core/MMU: Fix inverted condition in HostIsInstructionRAMAddress(). 2021-07-09 05:48:17 +02:00
Markus Wick cfcc994f6c Merge pull request #9840 from JosJuice/jitarm64-mffsx 
JitArm64: Implement mffsx
 2021-07-08 14:15:24 +02:00
Markus Wick a390d3f327 Merge pull request #9820 from JosJuice/jitarm64-simplify-addex 
JitArm64: Simplify addex/subfex
 2021-07-08 13:46:48 +02:00
Markus Wick f67f0488d2 Merge pull request #9844 from JosJuice/jitarm64-fctiwzx-constant 
JitArm64: Improve fctiwzx constant generation in double case
 2021-07-08 13:43:09 +02:00
Markus Wick 9df6f65834 Merge pull request #9867 from JosJuice/jitarm64-unconditional-exception-exit 
JitArm64: Add the ability to emit an unconditional exception exit
 2021-07-08 13:08:05 +02:00
Markus Wick 1827cb9cd8 Merge pull request #9874 from JosJuice/jitarm64-unconditional-farcode 
JitArm64: Get rid of an unconditional branch to farcode
 2021-07-08 13:01:21 +02:00
Markus Wick 98098edad7 Merge pull request #9859 from JosJuice/jitarm64-stwbrx-sthbrx 
JitArm64: Implement stwbrx/sthbrx
 2021-07-07 21:45:06 +02:00
JosJuice a6700a074d JitArm64: Get rid of an unconditional branch to farcode 
If a branch is unconditional, its target should not be in farcode,
since that defeats the purpose of farcode (putting seldom executed
code in farcode to keep it out of the icache when possible).
 2021-07-07 14:11:07 +02:00
Léo Lam 1450e97c28 Merge pull request #9522 from AdmiralCurtiss/host-read-optional 
Core/MMU: Add HostTryRead/HostTryWrite functions to allow specifying the desired address space, and return whether it succeeded.
 2021-07-07 12:32:47 +02:00
JosJuice 0642ff8b25 JitArm64: Check MSR.EE for external exceptions, not MSR.FE0 
Fixes a 58698b8380 regression. (The EXCEPTION_EXTERNAL_INT
immediate being wrong meant that we never took the branch,
masking the problem of the MSR.EE immediate being wrong...)
 2021-07-07 11:55:53 +02:00
Admiral H. Curtiss c292351faa Core/MMU: Add HostTryWrite*() functions. 2021-07-07 04:26:28 +02:00
Admiral H. Curtiss b59fcae70a Core/MMU: Add HostTryRead*() functions. 2021-07-07 04:26:28 +02:00
Léo Lam 21d75099fc Merge pull request #9866 from JosJuice/jitarm64-hardcoded-exceptions 
JitArm64: Don't hardcode exception constants
 2021-07-06 15:21:38 +02:00
JosJuice 1a64364ae3 JitArm64: Add the ability to emit an unconditional exception exit 
In cases where we already know that there is an exception,
either because we just checked for it or because we were
the ones that generated the exception to begin with,
we can skip the branch inside WriteExceptionExit.
 2021-07-06 11:33:46 +02:00
JosJuice 58698b8380 JitArm64: Don't hardcode exception constants 
Unlike most constants we emit in JitArm64, these constants are
*not* inherent to the CPU we're emulating, and can have whatever
values we want. Let's handle them more robustly, in case we
decide to change their values in the future.
 2021-07-05 23:05:30 +02:00
Pierre Bourdon e149ad4f0a treewide: convert GPLv2+ license info to SPDX tags 
SPDX standardizes how source code conveys its copyright and licensing
information. See https://spdx.github.io/spdx-spec/1-rationale/ . SPDX
tags are adopted in many large projects, including things like the Linux
kernel.
 2021-07-05 04:35:56 +02:00
JosJuice f666df72c0 JitArm64: Implement stwbrx/sthbrx 2021-07-03 12:21:45 +02:00
JosJuice d3ef5d4ca4 JitArm64: Fix lwbrx/lhbrx with optimized MMIO access 2021-07-01 13:38:26 +02:00
JosJuice e581d970d6 JitArm64: Fix MSVC warning '~': zero extending 'u32' to 'u64' 
While the third parameter of ANDI2R is u64, the upper half of
it does not get read if we're emitting a 32-bit instruction
(which we are doing here).
 2021-06-29 10:44:41 +02:00
Tilka 901a4fb5f4 Merge pull request #9811 from JosJuice/fprf-denormal-singles 
Fix FPRF handling of denormal singles
 2021-06-29 03:18:18 +01:00
Tilka 856c82aa24 Merge pull request #9851 from JosJuice/jitarm64-mfcr 
JitArm64: Handle SO and LT simultaneously in mfcr
 2021-06-29 02:01:31 +01:00
JosJuice 1df1f20c44 JitArm64: Handle SO and LT simultaneously in mfcr 2021-06-28 19:22:46 +02:00
Tilka bb2d576ecc Merge pull request #9849 from Tilka/x87 
x64Emitter: remove unused x87 instructions
 2021-06-28 17:53:54 +01:00
JosJuice 2ef2eee2e0 Merge pull request #9464 from Sintendo/jit64addxreloaded 
Jit64: addx revisited
 2021-06-28 13:53:44 +02:00
Tillmann Karras a68c1bf648 PowerPC: add enum values for emulator SO and LT shifts 2021-06-28 03:30:07 +01:00
Tillmann Karras 25a701aa1b PowerPC: move SO bit to a more convenient location 
Spacing the LT and SO bits like in the native PowerPC format makes it easier to
convert to that format (see mfcr).
 2021-06-28 03:06:45 +01:00
Tillmann Karras afb9398059 x64Emitter: remove unused x87 instructions 2021-06-28 02:56:37 +01:00
JosJuice ccd8233ea3 Jit64: Fix FPRF handling of denormal singles 2021-06-27 20:37:18 +02:00
JosJuice 8d2c069c34 Interpreter: Return float from ForceSingle 
Performance optimization, along with making the code a little
neater. Saves us from performing a single -> double -> single
conversion when calling UpdateFPRFSingle.
 2021-06-27 20:34:49 +02:00
JosJuice d56721ebb9 Interpreter: Fix FPRF handling of denormal singles 2021-06-27 20:34:49 +02:00
JosJuice def5666419 JitArm64: Fix FPRF handling of denormal singles 
The interpreter was wrong after all. Hardware verified.
 2021-06-27 20:34:49 +02:00
Tilka aff39af5fb Merge pull request #9810 from JosJuice/fprf-cmp-mask 
Jits: Fix fcmpX FPRF mask
 2021-06-27 19:32:19 +01:00
Tilka 4166567f92 Merge pull request #9812 from JosJuice/fprf-x64-neg-zero 
Jit64: Fix FPRF non-SSE4.1 handling of negative zero
 2021-06-27 19:21:51 +01:00
Sintendo 7de4623d48 Jit64: mtfsfx - Optimized masking 
The masking logic can be eliminated when the mask is known to be all
ones. This case is very common.

Before:
66 48 0F 7E F0       movq        rax,xmm6
8B 55 5C             mov         edx,dword ptr [rbp+5Ch]
83 E0 FF             and         eax,0FFFFFFFFh
83 E2 00             and         edx,0
0B C2                or          eax,edx
89 45 5C             mov         dword ptr [rbp+5Ch],eax
48 8D 15 C3 3C FE 01 lea         rdx,[19520020h]
83 E0 07             and         eax,7
0F AE 14 82          ldmxcsr     dword ptr [rdx+rax*4]

After:
66 48 0F 7E F0       movq        rax,xmm6
89 45 5C             mov         dword ptr [rbp+5Ch],eax
48 8D 15 2A D1 FD 01 lea         rdx,[19440000h]
83 E0 07             and         eax,7
0F AE 14 82          ldmxcsr     dword ptr [rdx+rax*4]
 2021-06-26 17:31:31 +02:00
JosJuice 36798b18e8 JitArm64: Improve fctiwzx constant generation in double case 
If we already have to use a GPR, we might as well take advantage
of the nice immediate encodings provided by GPR ORR. This is
faster, smaller, and saves a register.
 2021-06-26 15:41:23 +02:00
JosJuice 8cd37e040a JitArm64: Implement mffsx 
Part 2 of implementing the FPSCR system register instructions.
 2021-06-24 12:00:58 +02:00