Yaya48
ebb753d09a
Save the remaining ARM JIT and MMU/cache optimizations, accurate Starlet timer and Wiimote report cadence, opt-in PPC event tracing, and full texture hashing in the LLE launcher. Include regression coverage and exclude local profiling artifacts. Validation: 127 targeted tests from 15 suites passed, with one disabled test. Includes the current user-tested source state following the persistent NAND milestone.
317 lines
10 KiB
C++
317 lines
10 KiB
C++
// Copyright 2026 Dolphin Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <array>
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#include <memory>
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#include "Common/x64ABI.h"
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#include "Core/ConfigManager.h"
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#include "Core/Core.h"
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#include "Core/HW/Memmap.h"
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#include "Core/PowerPC/Jit64/Jit.h"
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#include "Core/PowerPC/Jit64Common/Jit64AsmCommon.h"
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#include "Core/PowerPC/Jit64Common/Jit64Constants.h"
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#include "Core/PowerPC/MMU.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/System.h"
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#include <gtest/gtest.h>
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namespace
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{
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using namespace Gen;
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// Execute the real SafeLoad/SafeWrite emitter, including its fallback and register contract.
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// Testing only the C++ MMU helpers cannot detect corruption introduced at the native call site.
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class DCacheCode : public CommonAsmRoutines
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{
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public:
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explicit DCacheCode(Core::System& system) : CommonAsmRoutines(jit), jit(system)
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{
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jit.jo = {};
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jit.js = {};
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AllocCodeSpace(512 * 1024);
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old_read = dcache32_read_hit_dbat;
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old_write = dcache32_write_hit_dbat;
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dcache32_read_hit_dbat = AlignCode4();
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GenDCache32Hit(false);
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dcache32_write_hit_dbat = AlignCode4();
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GenDCache32Hit(true);
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}
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~DCacheCode() override
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{
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dcache32_read_hit_dbat = old_read;
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dcache32_write_hit_dbat = old_write;
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}
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void Access(bool write, u32 address, u32 value, X64Reg address_reg, X64Reg value_reg,
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s32 offset = 0, int flags = 0)
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{
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run = reinterpret_cast<void (*)()>(AlignCode4());
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ABI_PushRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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MOV(64, R(RPPCSTATE), ImmPtr(reinterpret_cast<u8*>(&jit.m_ppc_state) + 0x80));
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MOV(32, R(RDX), Imm32(0x12345678));
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MOV(32, R(RCX), Imm32(0x87654321));
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MOV(32, R(address_reg), Imm32(address));
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if (write)
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MOV(32, R(value_reg), Imm32(value));
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const BitSet32 live{RCX, RDX, R8, R9};
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if (flags & SAFE_LOADSTORE_NO_PROLOG)
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SUB(64, R(RSP), Imm8(8));
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if (write)
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SafeWriteRegToReg(value_reg, address_reg, 32, offset, live, flags);
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else
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SafeLoadToReg(value_reg, R(address_reg), 32, offset, live, false, flags);
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if (flags & SAFE_LOADSTORE_NO_PROLOG)
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ADD(64, R(RSP), Imm8(8));
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MOV(64, R(R11), ImmPtr(result.data()));
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for (const auto reg : {RAX, RCX, RDX, R8, R9})
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MOV(64, MDisp(R11, static_cast<int>(reg) * sizeof(u64)), R(reg));
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ABI_PopRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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RET();
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ASSERT_FALSE(HasWriteFailed());
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run();
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}
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std::array<u64, 16> result{};
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void (*run)() = nullptr;
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Jit64 jit;
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const u8* old_read;
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const u8* old_write;
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};
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class Jit64DCache : public testing::Test
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{
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protected:
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static void SetUpTestSuite()
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{
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SConfig::Init();
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auto& system = Core::System::GetInstance();
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system.SetIsWii(true);
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system.GetMemory().Init();
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Core::DeclareAsCPUThread();
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system.GetPPCState().dCache.Init(system.GetMemory());
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}
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static void TearDownTestSuite()
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{
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auto& system = Core::System::GetInstance();
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system.GetPPCState().m_enable_dcache = false;
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system.GetMemory().Shutdown();
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system.SetIsWii(false);
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Core::UndeclareAsCPUThread();
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SConfig::Shutdown();
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}
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void SetUp() override
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{
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state.dCache.Reset();
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state.m_enable_dcache = true;
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state.msr.DR = 1;
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state.feature_flags = FEATURE_FLAG_MSR_DR;
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state.Exceptions = 0;
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state.spr[SPR_HID0] = 0;
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bats.fill(0);
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bats[0x80000000 >> PowerPC::BAT_INDEX_SHIFT] = PowerPC::BAT_MAPPED_BIT;
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bats[0x90000000 >> PowerPC::BAT_INDEX_SHIFT] = 0x10000000 | PowerPC::BAT_MAPPED_BIT;
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code = std::make_unique<DCacheCode>(system);
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}
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void TearDown() override { code.reset(); }
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Core::System& system = Core::System::GetInstance();
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PowerPC::PowerPCState& state = system.GetPPCState();
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PowerPC::MMU& mmu = system.GetMMU();
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Memory::MemoryManager& memory = system.GetMemory();
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PowerPC::BatTable& bats = const_cast<PowerPC::BatTable&>(mmu.GetDBATTable());
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std::unique_ptr<DCacheCode> code;
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};
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TEST_F(Jit64DCache, StoreMissRetainsAddressInRDX)
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{
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// The data is deliberately also a mapped address: a broken fallback writes there instead.
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memory.Write_U32(0, 0x1000);
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memory.Write_U32(0, 0x4000);
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code->Access(true, 0x80001000, 0x80004000, RDX, RCX);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x80001000), 0x80004000);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x80004000), 0U);
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EXPECT_EQ(code->result[RDX], 0x80001000);
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EXPECT_EQ(code->result[RCX], 0x80004000);
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}
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TEST_F(Jit64DCache, LoadMissRetainsAddressInRDX)
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{
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memory.Write_U32(0x89abcdef, 0x1000);
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code->Access(false, 0x80001000, 0, RDX, R8);
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EXPECT_EQ(code->result[R8], 0x89abcdef);
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EXPECT_EQ(code->result[RDX], 0x80001000);
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}
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TEST_F(Jit64DCache, HitPreservesLiveScratchRegisters)
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{
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mmu.WriteForJit<u32>(0xffffffff, 0x80001000);
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code->Access(false, 0x80001000, 0, R9, R8);
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EXPECT_EQ(code->result[R8], 0xffffffff);
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EXPECT_EQ(code->result[RDX], 0x12345678U);
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EXPECT_EQ(code->result[RCX], 0x87654321U);
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code->Access(true, 0x80001000, 0x11223344, R9, R8);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x80001000), 0x11223344U);
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EXPECT_EQ(code->result[RDX], 0x12345678U);
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EXPECT_EQ(code->result[RCX], 0x87654321U);
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}
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TEST_F(Jit64DCache, PhysicalAccessIgnoresDBAT)
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{
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state.msr.DR = 0;
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state.feature_flags = CPUEmuFeatureFlags{};
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bats[0] = 0x20000 | PowerPC::BAT_MAPPED_BIT;
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mmu.WriteForJit<u32>(0x11111111, 0x1000);
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mmu.WriteForJit<u32>(0x22222222, 0x21000);
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code->Access(false, 0x1000, 0, R9, R8);
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EXPECT_EQ(code->result[R8], 0x11111111U);
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code->Access(true, 0x1000, 0x33333333, R9, R8);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x1000), 0x33333333U);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x21000), 0x22222222U);
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}
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TEST_F(Jit64DCache, LoadRegisterAndOffsetCombinations)
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{
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for (const bool hit : {false, true})
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{
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for (const auto address_reg : {RAX, RCX, RDX, R8, R9})
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{
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for (const auto value_reg : {RAX, RCX, RDX, R8, R9})
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{
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for (const s32 offset : {0, 4, -4})
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{
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SCOPED_TRACE(testing::Message()
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<< hit << ' ' << address_reg << ' ' << value_reg << ' ' << offset);
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state.dCache.Reset();
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memory.Write_U32(0xfedcba98, 0x1020);
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if (hit)
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ASSERT_EQ(mmu.ReadForJit<u32>(0x80001020), 0xfedcba98);
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code->Access(false, 0x80001020 - offset, 0, address_reg, value_reg, offset);
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EXPECT_EQ(code->result[value_reg], 0xfedcba98);
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}
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}
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}
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}
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}
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TEST_F(Jit64DCache, StoreRegisterAndOffsetCombinations)
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{
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for (const bool hit : {false, true})
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{
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for (const auto address_reg : {RAX, RCX, RDX, R8, R9})
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{
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for (const auto value_reg : {RCX, RDX, R8, R9})
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{
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if (address_reg == value_reg)
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continue;
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for (const s32 offset : {0, 4, -4})
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{
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SCOPED_TRACE(testing::Message()
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<< hit << ' ' << address_reg << ' ' << value_reg << ' ' << offset);
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state.dCache.Reset();
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memory.Write_U32(0, 0x1020);
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if (hit)
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ASSERT_EQ(mmu.ReadForJit<u32>(0x80001020), 0U);
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code->Access(true, 0x80001020 - offset, 0xfedcba98, address_reg, value_reg, offset,
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EmuCodeBlock::SAFE_LOADSTORE_CLOBBER_RSCRATCH_INSTEAD_OF_ADDR);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x80001020), 0xfedcba98);
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EXPECT_EQ(code->result[value_reg], 0xfedcba98);
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}
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}
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}
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}
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}
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TEST_F(Jit64DCache, SplitLineAndPageAccess)
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{
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for (const u32 offset : {29U, 30U, 31U, 4093U, 4094U, 4095U})
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{
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SCOPED_TRACE(offset);
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const u32 address = 0x80001000 + offset;
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mmu.WriteForJit<u32>(0x11223344, address);
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code->Access(false, address, 0, RDX, R8);
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EXPECT_EQ(code->result[R8], 0x11223344U);
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code->Access(true, address, 0x55667788, RDX, RCX);
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EXPECT_EQ(mmu.ReadForJit<u32>(address), 0x55667788U);
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}
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}
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TEST_F(Jit64DCache, InhibitedBATBypassesCachedData)
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{
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mmu.WriteForJit<u32>(0x11111111, 0x80001000);
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memory.Write_U32(0x22222222, 0x1000);
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bats[0x80000000 >> PowerPC::BAT_INDEX_SHIFT] |= PowerPC::BAT_WI_BIT;
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code->Access(false, 0x80001000, 0, RDX, R8);
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EXPECT_EQ(code->result[R8], 0x22222222U);
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code->Access(true, 0x80001000, 0x33333333, RDX, RCX);
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EXPECT_EQ(memory.Read_U32(0x1000), 0x33333333U);
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bats[0x80000000 >> PowerPC::BAT_INDEX_SHIFT] &= ~PowerPC::BAT_WI_BIT;
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EXPECT_EQ(mmu.ReadForJit<u32>(0x80001000), 0x11111111U);
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}
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TEST_F(Jit64DCache, SharedRoutineStackAndDRFlag)
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{
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// Shared paired-load routines are emitted without a known block's feature flags and run
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// with a return address on the stack. DR_ON is their explicit translation contract.
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state.feature_flags = CPUEmuFeatureFlags{};
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constexpr int flags = EmuCodeBlock::SAFE_LOADSTORE_NO_PROLOG |
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EmuCodeBlock::SAFE_LOADSTORE_NO_UPDATE_PC |
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EmuCodeBlock::SAFE_LOADSTORE_DR_ON;
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memory.Write_U32(0x89abcdef, 0x1000);
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for (int repeat = 0; repeat < 2; ++repeat)
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{
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code->Access(false, 0x80001000, 0, RDX, R8, 0, flags);
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EXPECT_EQ(code->result[R8], 0x89abcdef);
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code->Access(true, 0x80001000, 0x89abcdef, RDX, RCX, 0, flags);
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EXPECT_EQ(mmu.ReadForJit<u32>(0x80001000), 0x89abcdef);
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}
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}
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TEST_F(Jit64DCache, NativePLRUAndDirtyStateMatchMMU)
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{
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for (const u32 base : {0x80000000U, 0x90000000U})
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{
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state.dCache.Reset();
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constexpr u32 set = 126;
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for (u32 way = 0; way < PowerPC::CACHE_WAYS; ++way)
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mmu.WriteForJit<u32>(0xffffffff, base + way * 4096 + set * 32);
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for (u32 way = 0; way < PowerPC::CACHE_WAYS; ++way)
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{
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const u32 address = base + way * 4096 + set * 32;
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for (const bool write : {false, true})
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{
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code->Access(write, address, 0xffffffff, RDX, R8);
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for (u32 old_plru = 0; old_plru < 128; ++old_plru)
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{
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SCOPED_TRACE(testing::Message() << base << ' ' << way << ' ' << write << ' ' << old_plru);
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auto& cache = state.dCache;
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cache.plru[set] = static_cast<u8>(old_plru);
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cache.modified[set] = 0x80;
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if (write)
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ASSERT_TRUE(mmu.TryWriteDCache32ForJit(0xffffffff, address));
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else
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ASSERT_EQ(mmu.TryReadDCache32ForJit(address), 0x100000000ULL);
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const auto expected_plru = cache.plru[set];
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const auto expected_dirty = cache.modified[set];
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const auto expected_data = cache.data[set];
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cache.plru[set] = static_cast<u8>(old_plru);
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cache.modified[set] = 0x80;
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code->run();
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EXPECT_EQ(cache.plru[set], expected_plru);
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EXPECT_EQ(cache.modified[set], expected_dirty);
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EXPECT_EQ(cache.data[set], expected_data);
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if (!write)
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EXPECT_EQ(code->result[R8], 0xffffffff);
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}
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}
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}
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}
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}
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} // namespace
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