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dolphin/docs/StarletOS_Checkpoint.json
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{
"recordedAt": "2026-10-03",
"purpose": "Publish the exact existing StarletOS integration, without emulator behavior changes",
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},
"updates": [
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal L2: IPC request/reply metadata trace while the original IOS runs (DOLPHIN_IPC_TRACE=1); no behavior change otherwise",
"files": [
"Source/Core/Core/HW/WII_IPC.cpp"
]
},
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal M1: REV_BOOTSTRAP_WIIMOTE=1 gives a bootstrap-ELF (Revolution) session the emulated Wii Remotes with the identity paired in the attached NAND; never writes the NAND; off by default",
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]
},
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal M1e: the IPC trace also prints the paths named by filesystem IOCTLs (64-byte path, 76-byte record at +6, rename pair, first IOCTLV vector of 64 bytes); paths only",
"files": [
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]
},
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal F1: REV_WATCH=start:size[,...] logs Starlet CPU stores (instruction address, LR) and device DMA writes in those physical ranges; the ARM JIT routes accesses in watched ranges to its bus slow path and records the instruction address there; off by default",
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]
},
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal H1: with REV_WATCH, a shadow of each watched range (Starlet stores and device DMA); Starlet reads that differ from it (REVWATCH DIFF) and IPC-reply audits (REVWATCH AUDIT) reveal other writers; register-list transfers whose virtual range overlaps a watched range run through the architectural helper and log their translation (REVWATCH LDM/STM)",
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]
},
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal I1: the ARM interpreter executes the ARMv5TE enhanced DSP instructions (SMLAxy, SMLAWy, SMULWy, SMLALxy, SMULxy, QADD, QSUB, QDADD, QDSUB, Q flag), previously decoded as compare data processing that wrote no register; the JIT leaves them to the interpreter; test ARMv5TEEnhancedDSPInstructions",
"files": [
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"Source/Core/Core/IOS/Starlet/ARMCore.h",
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]
},
{
"recordedAt": "2026-10-06",
"purpose": "StarletOS Phase 11 proposal J1: with DOLPHIN_IPC_TRACE=1 and DOLPHIN_HW_WINDOW=1, Broadway hardware register accesses (MMU MMIO reads and writes, PC) are logged as HWTRACE from the reply to an IOCTL 0x28 32/32 request until the next IPC request; no inlined MMIO reads while requested",
"files": [
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"Source/Core/Core/HW/WII_IPC.h",
"Source/Core/Core/PowerPC/MMU.cpp"
]
}
]
}
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