Yaya48
c230971f07
Preserve formatted NAND boot and Wii Remote pairing, add DMA/SRAM conformance tests and a Wii comparison probe. Keep P1 profiling tools and native update A/B evidence; reject the unhelpful targeted SRAM shortcut.
442 lines
16 KiB
C++
442 lines
16 KiB
C++
// Copyright 2026 Dolphin Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <algorithm>
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#include <array>
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#include <iomanip>
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#include <memory>
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#include <optional>
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#include <gtest/gtest.h>
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#include "Common/Swap.h"
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#include "Core/Core.h"
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#include "Core/HW/WII_IPC.h"
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#include "Core/IOS/Starlet/ARMCore.h"
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#include "Core/IOS/Starlet/StarletMemory.h"
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#include "Core/System.h"
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namespace IOS::LLE
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{
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#if defined(_M_X86_64)
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namespace
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{
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// Only code and page tables use synthetic RAM. Data reads exercise the actual SRAM/boot0 bus,
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// without initializing any firmware, NAND image, profile, or live peripheral scheduler.
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class SRAMReadBus final : public ARMBus
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{
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public:
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SRAMReadBus() : memory(Core::System::GetInstance())
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{
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memory.Reset();
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for (u32 i = 0; i < 0x18000; ++i)
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memory.GetFastmemSRAMBase()[i] = static_cast<u8>((i * 13) ^ (i >> 8) ^ 0xa5);
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}
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u8 Read8(u32 address) override
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{
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if (address < ram.size())
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return ram[address];
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++data_reads;
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return memory.Read8(address);
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}
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u16 Read16(u32 address) override
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{
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if (address < ram.size())
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return ARMBus::Read16(address);
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++data_reads;
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return memory.Read16(address);
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}
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u32 Read32(u32 address) override
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{
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if (address < ram.size())
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return ARMBus::Read32(address);
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++data_reads;
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return memory.Read32(address);
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}
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void Write8(u32 address, u8 value) override
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{
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if (address < ram.size())
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ram[address] = value;
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else
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memory.Write8(address, value);
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}
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void Write16(u32 address, u16 value) override
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{
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if (address < ram.size())
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ARMBus::Write16(address, value);
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else
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memory.Write16(address, value);
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}
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void Write32(u32 address, u32 value) override
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{
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if (address < ram.size())
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ARMBus::Write32(address, value);
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else
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memory.Write32(address, value);
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}
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u8* GetFastmemBase() const override { return const_cast<u8*>(ram.data()); }
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u8* GetFastmemSRAMBase() const override { return memory.GetFastmemSRAMBase(); }
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const bool* GetFastmemBoot0Mapped() const override { return memory.GetFastmemBoot0Mapped(); }
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const bool* GetFastmemSRAMSplitMode() const override { return memory.GetFastmemSRAMSplitMode(); }
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const u8* GetDirectMemoryPointer(u32 address, u32 size) const override
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{
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if (address < ram.size() && size <= ram.size() - address)
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return ram.data() + address;
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return memory.GetDirectMemoryPointer(address, size);
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}
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void SetMapping(bool split, bool boot0)
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{
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memory.Write32(0x0d800060, split ? 0x20 : 0); // HW_SRNPROT
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memory.Write32(0x0d80018c, boot0 ? 0 : 0x1000); // HW_BOOT0
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}
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void InstallReads(bool thumb, bool big_endian)
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{
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if (thumb)
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{
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constexpr std::array<u16, 6> code = {
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0x6830, // ldr r0, [r6]
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0x7831, // ldrb r1, [r6]
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0x8832, // ldrh r2, [r6]
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0x57f3, // ldrsb r3, [r6, r7]
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0x5ff4, // ldrsh r4, [r6, r7]
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0xe7fe, // b .
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};
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for (u32 i = 0; i < code.size(); ++i)
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Write16(i * 2, big_endian ? code[i] : Common::swap16(code[i]));
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}
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else
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{
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constexpr std::array<u32, 6> code = {
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0xe5960000, // ldr r0, [r6]
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0xe5d61000, // ldrb r1, [r6]
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0xe1d620b0, // ldrh r2, [r6]
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0xe1d630d0, // ldrsb r3, [r6]
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0xe1d640f0, // ldrsh r4, [r6]
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0xeafffffe, // b .
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};
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for (u32 i = 0; i < code.size(); ++i)
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Write32(i * 4, big_endian ? code[i] : Common::swap32(code[i]));
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}
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}
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void InstallStores(bool thumb, bool big_endian)
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{
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if (thumb)
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{
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constexpr std::array<u16, 4> code = {
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0x6030, // str r0, [r6]
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0x7131, // strb r1, [r6, #4]
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0x80f2, // strh r2, [r6, #6]
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0xe7fe, // b .
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};
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for (u32 i = 0; i < code.size(); ++i)
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Write16(i * 2, big_endian ? code[i] : Common::swap16(code[i]));
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}
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else
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{
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constexpr std::array<u32, 4> code = {
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0xe5860000, // str r0, [r6]
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0xe5c61004, // strb r1, [r6, #4]
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0xe1c620b6, // strh r2, [r6, #6]
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0xeafffffe, // b .
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};
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for (u32 i = 0; i < code.size(); ++i)
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Write32(i * 4, big_endian ? code[i] : Common::swap32(code[i]));
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}
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}
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StarletMemory memory;
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std::array<u8, 0x8000> ram{};
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u64 data_reads = 0;
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};
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class StarletSRAMRead : public testing::TestWithParam<bool>
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{
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protected:
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void SetUp() override
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{
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Core::DeclareAsCPUThread();
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Core::System::GetInstance().GetWiiIPC().Reset();
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}
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static void Prepare(ARMCore& core, bool thumb, bool big_endian, u32 address)
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{
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if (core.IsBigEndian() != big_endian)
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core.SetBigEndian(big_endian);
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core.SetCPSR(static_cast<u32>(ARMCore::Mode::Supervisor) | (thumb ? ARMCore::CPSR_T : 0));
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for (u32 i = 0; i < 16; ++i)
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core.SetRegister(i, 0);
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core.SetRegister(6, address);
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}
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};
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TEST_P(StarletSRAMRead, NewlyProfiledPagesAvoidDataBusCalls)
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{
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for (const bool thumb : {false, true})
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{
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for (const bool big_endian : {false, true})
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{
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auto bus = std::make_unique<SRAMReadBus>();
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bus->SetMapping(true, false);
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bus->InstallReads(thumb, big_endian);
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ARMCore core(*bus, GetParam());
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core.SetJitEnabled(true);
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for (const u32 base : {0x0d400000u, 0xfff00000u, 0xfffe0000u})
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{
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for (const u32 page : {0x01u, 0x02u, 0x04u, 0x13u, 0x15u, 0x16u, 0x1au, 0x1cu, 0x1du})
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{
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const u32 address = base + page * 0x1000;
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SCOPED_TRACE(testing::Message() << "thumb=" << thumb << " be=" << big_endian
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<< " address=" << std::hex << address);
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Prepare(core, thumb, big_endian, address);
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bus->data_reads = 0;
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ASSERT_EQ(core.RunCycles(6), 6u);
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ASSERT_EQ(core.GetLastUndefinedInstruction(), 0u);
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ASSERT_EQ(bus->data_reads, 0u);
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EXPECT_EQ(core.GetRegister(0), big_endian ? bus->memory.Read32(address) :
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Common::swap32(bus->memory.Read32(address)));
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}
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}
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EXPECT_EQ(core.GetJitSlowReadCount(), 0u);
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EXPECT_EQ(core.GetJitFallbackInstructionCount(), 0u);
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EXPECT_EQ(core.GetJitCompiledBlockCount(), 1u);
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}
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}
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}
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TEST_P(StarletSRAMRead, SizedNativeStoresMatchInterpreterAcrossMappings)
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{
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for (const bool thumb : {false, true})
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{
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for (const bool big_endian : {false, true})
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{
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auto reference_bus = std::make_unique<SRAMReadBus>();
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auto native_bus = std::make_unique<SRAMReadBus>();
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reference_bus->InstallStores(thumb, big_endian);
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native_bus->InstallStores(thumb, big_endian);
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ARMCore reference(*reference_bus);
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ARMCore native(*native_bus, GetParam());
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native.SetJitEnabled(true);
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for (const bool split : {false, true, false})
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{
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for (const bool boot0 : {false, true, false})
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{
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reference_bus->SetMapping(split, boot0);
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native_bus->SetMapping(split, boot0);
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for (const u32 base : {0x0d400000U, 0xfff00000U, 0xfffe0000U})
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{
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for (u32 page = 0; page < 32; ++page)
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{
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for (const u32 offset : {0U, 1U, 2U, 3U, 0xff8U, 0xffcU, 0xffeU, 0xfffU})
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{
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const u32 address = base + page * 0x1000 + offset;
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if (address > 0xfffffff7U)
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continue; // Do not wrap a test data store into synthetic guest code.
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SCOPED_TRACE(testing::Message()
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<< "thumb=" << thumb << " be=" << big_endian << " split=" << split
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<< " boot0=" << boot0 << " address=" << std::hex << address);
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for (ARMCore* core : {&reference, &native})
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{
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Prepare(*core, thumb, big_endian, address);
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core->SetRegister(0, 0x12345678);
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core->SetRegister(1, 0x9abcdef0);
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core->SetRegister(2, 0x7e3dac12);
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ASSERT_EQ(core->RunCycles(4), 4U);
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ASSERT_EQ(core->GetLastUndefinedInstruction(), 0U);
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}
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for (u32 reg = 0; reg < 16; ++reg)
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ASSERT_EQ(native.GetRegister(reg), reference.GetRegister(reg));
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ASSERT_EQ(native.GetCPSR(), reference.GetCPSR());
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ASSERT_TRUE(std::equal(reference_bus->memory.GetFastmemSRAMBase(),
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reference_bus->memory.GetFastmemSRAMBase() + 0x18000,
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native_bus->memory.GetFastmemSRAMBase()));
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for (u32 byte = 0; byte < 8; ++byte)
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ASSERT_EQ(native_bus->Read8(address + byte),
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reference_bus->Read8(address + byte));
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}
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}
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}
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}
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}
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}
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}
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}
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TEST_P(StarletSRAMRead, MatchesInterpreterAcrossLiveMappingsAliasesAndBoundaries)
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{
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for (const bool thumb : {false, true})
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{
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for (const bool big_endian : {false, true})
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{
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auto interpreter_bus = std::make_unique<SRAMReadBus>();
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auto jit_bus = std::make_unique<SRAMReadBus>();
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interpreter_bus->InstallReads(thumb, big_endian);
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jit_bus->InstallReads(thumb, big_endian);
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ARMCore interpreter(*interpreter_bus);
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ARMCore jit(*jit_bus, GetParam());
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jit.SetJitEnabled(true);
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std::array<u8, 0x18000> original;
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std::copy_n(jit_bus->GetFastmemSRAMBase(), original.size(), original.begin());
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std::optional<u64> compiled_blocks;
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// Toggle the hardware state while reusing the same compiled code: guards must consult
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// live boot0/split latches, not their values at compilation time.
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for (const bool split : {false, true, false})
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{
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for (const bool boot0 : {false, true, false})
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{
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interpreter_bus->SetMapping(split, boot0);
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jit_bus->SetMapping(split, boot0);
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for (const u32 base : {0x0d400000u, 0xfff00000u, 0xfffe0000u})
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{
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for (u32 page = 0; page < 32; ++page)
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{
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for (const u32 offset :
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{0u, 1u, 2u, 3u, 0x3fdu, 0x3feu, 0x3ffu, 0xffcu, 0xffdu, 0xffeu, 0xfffu})
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{
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const u32 address = base + page * 0x1000 + offset;
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if (address > 0xfffffffcu)
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continue; // Exclude address-space wrap into the synthetic code buffer.
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SCOPED_TRACE(testing::Message()
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<< "thumb=" << thumb << " be=" << big_endian << " split=" << split
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<< " boot0=" << boot0 << " address=" << std::hex << address);
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Prepare(interpreter, thumb, big_endian, address);
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Prepare(jit, thumb, big_endian, address);
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ASSERT_EQ(interpreter.RunCycles(6), 6u);
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ASSERT_EQ(jit.RunCycles(6), 6u);
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ASSERT_EQ(jit.GetLastUndefinedInstruction(), 0u);
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for (u32 reg = 0; reg < 16; ++reg)
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ASSERT_EQ(jit.GetRegister(reg), interpreter.GetRegister(reg)) << "r" << reg;
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ASSERT_EQ(jit.GetCPSR(), interpreter.GetCPSR());
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}
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}
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}
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// Unaligned fallbacks also compile continuations. Once the first boundary sweep has
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// warmed them, changing the hardware mapping must reuse those blocks, not rebuild them.
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if (!compiled_blocks)
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compiled_blocks = jit.GetJitLifetimeCompiledBlockCount();
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else
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EXPECT_EQ(jit.GetJitLifetimeCompiledBlockCount(), *compiled_blocks);
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}
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}
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EXPECT_TRUE(std::equal(original.begin(), original.end(), jit_bus->GetFastmemSRAMBase()));
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EXPECT_TRUE(
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std::equal(original.begin(), original.end(), interpreter_bus->GetFastmemSRAMBase()));
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}
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}
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}
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TEST_P(StarletSRAMRead, PreservedBlockUsesRemappedSRAMAfterGuestTLBInvalidation)
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{
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auto bus = std::make_unique<SRAMReadBus>();
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bus->SetMapping(true, false);
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bus->Write32(0, 0xe5960000); // ldr r0, [r6]
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bus->Write32(4, 0xeafffffe); // b .
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bus->Write32(0x40, 0xee080f17); // mcr p15, 0, r0, c8, c7, 0 (invalidate unified TLB)
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bus->Write32(0x4000, 0x00000c02); // Identity section for code/page tables.
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bus->Write32(0x4c00, 0x00005001); // VA 0x30000000 -> coarse page table at 0x5000.
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bus->Write32(0x5000, 0x0d404ff2); // Small page -> SRAM B, aperture page 04.
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bus->memory.Write32(0x0d404000, 0x12345678);
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bus->memory.Write32(0xffff6000, 0x87654321);
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ARMCore core(*bus, GetParam());
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core.GetCP15State().translation_table_base = 0x4000;
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core.GetCP15State().domain_access_control = 3;
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core.GetCP15State().control |= 1;
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core.SetRegister(6, 0x30000000);
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core.SetJitEnabled(true);
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ASSERT_EQ(core.RunCycles(2), 2u);
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ASSERT_EQ(core.GetRegister(0), 0x12345678u);
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const auto old_blocks = core.GetJitCompiledBlockCount();
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bus->Write32(0x5000, 0xffff6ff2); // Remap to SRAM A, aperture page 16.
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core.SetRegister(15, 0x40);
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ASSERT_EQ(core.RunCycles(1), 1u);
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core.SetRegister(15, 0);
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ASSERT_EQ(core.RunCycles(2), 2u);
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EXPECT_EQ(core.GetRegister(0), 0x87654321u);
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EXPECT_EQ(core.GetJitCompiledBlockCount(), old_blocks + 1);
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EXPECT_EQ(core.GetJitSlowReadCount(), 0u);
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}
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TEST_P(StarletSRAMRead, OptionalProfilingPreservesBusCountsResultsAndReset)
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{
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for (const bool thumb : {false, true})
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{
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for (const bool big_endian : {false, true})
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{
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for (const u32 address : {0xfff1f000U, 0x0d800214U})
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{
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auto bus = std::make_unique<SRAMReadBus>();
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auto reference_bus = std::make_unique<SRAMReadBus>();
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for (SRAMReadBus* target : {bus.get(), reference_bus.get()})
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{
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target->SetMapping(true, false);
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target->memory.Write32(address, 0x89abcdef);
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if (thumb)
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{
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target->Write16(0, big_endian ? 0x6830 : Common::swap16(0x6830)); // ldr r0,[r6]
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target->Write16(2, big_endian ? 0x6030 : Common::swap16(0x6030)); // str r0,[r6]
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target->Write16(4, big_endian ? 0xe7fc : Common::swap16(0xe7fc)); // b 0
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}
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else
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{
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target->Write32(0, big_endian ? 0xe5960000 : Common::swap32(0xe5960000));
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target->Write32(4, big_endian ? 0xe5860000 : Common::swap32(0xe5860000));
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target->Write32(8, big_endian ? 0xeafffffc : Common::swap32(0xeafffffc));
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}
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}
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ARMCore core(*bus, GetParam());
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ARMCore reference(*reference_bus);
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EXPECT_FALSE(reference.IsJitMemoryProfilingEnabled());
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core.SetJitEnabled(true);
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// Recompile after reset and endian changes with the same host-only profiling choice.
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for (int reset = 0; reset < 2; ++reset)
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{
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core.Reset();
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reference.Reset();
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EXPECT_EQ(core.IsJitMemoryProfilingEnabled(), GetParam());
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const u64 reads_before = core.GetJitSlowReadCount();
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const u64 writes_before = core.GetJitSlowWriteCount();
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for (ARMCore* cpu : {&core, &reference})
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{
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Prepare(*cpu, thumb, big_endian, address);
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ASSERT_EQ(cpu->RunCycles(768), 768U);
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}
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EXPECT_EQ(core.GetJitSlowReadCount() - reads_before, 256U);
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EXPECT_EQ(core.GetJitSlowWriteCount() - writes_before, 256U);
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for (u32 reg = 0; reg < 16; ++reg)
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EXPECT_EQ(core.GetRegister(reg), reference.GetRegister(reg));
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EXPECT_EQ(core.GetCPSR(), reference.GetCPSR());
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EXPECT_EQ(bus->memory.Read32(address), reference_bus->memory.Read32(address));
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EXPECT_EQ(bus->memory.Read32(address), 0x89abcdefU);
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const auto samples = core.TakeHotJitSlowMemorySamples(8);
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if (GetParam())
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{
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ASSERT_EQ(samples.size(), 2U);
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for (const auto& [key, count] : samples)
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{
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EXPECT_EQ(static_cast<u32>(key), address);
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EXPECT_EQ(count, 1U);
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}
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EXPECT_GT(address == 0xfff1f000 ? core.GetJitSlowSRAMAccessCount() :
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core.GetJitSlowMMIOAccessCount(),
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0U);
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}
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else
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{
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EXPECT_TRUE(samples.empty());
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EXPECT_EQ(core.GetJitSlowSRAMAccessCount(), 0U);
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EXPECT_EQ(core.GetJitSlowMMIOAccessCount(), 0U);
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EXPECT_EQ(core.GetJitSlowSRAMPageAccessCount(0x1f), 0U);
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}
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}
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|
}
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}
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}
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}
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INSTANTIATE_TEST_SUITE_P(MemoryProfiling, StarletSRAMRead, testing::Bool());
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} // namespace
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#endif
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} // namespace IOS::LLE
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