Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
106 lines
3.5 KiB
C
106 lines
3.5 KiB
C
/*
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* Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd
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* Copyright (C) 2025 NVIDIA
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* Written by Nicolin Chen, Shameer Kolothum
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_ARM_SMMUV3_ACCEL_H
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#define HW_ARM_SMMUV3_ACCEL_H
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#include "hw/arm/smmu-common.h"
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#include "hw/arm/smmuv3.h"
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#include "system/iommufd.h"
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#ifdef CONFIG_LINUX
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#include <linux/iommufd.h>
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#endif
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typedef enum SMMUv3AccelCmdqvType {
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SMMUV3_CMDQV_NONE = 0,
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SMMUV3_CMDQV_TEGRA241,
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} SMMUv3AccelCmdqvType;
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/*
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* CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to
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* support multiple VCMDQs with virtualization capabilities.
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* CMDQV specific behavior is factored behind this ops interface.
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*/
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typedef struct SMMUv3AccelCmdqvOps {
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/**
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* @probe: Mandatory. Vendor-specific device probing.
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*/
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bool (*probe)(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **errp);
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/**
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* @init: Optional callback. Initialize CMDQV hardware.
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*/
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bool (*init)(SMMUv3State *s, Error **errp);
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/**
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* @alloc_viommu: Mandatory. Allocate CMDQV viommu resources.
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*/
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bool (*alloc_viommu)(SMMUv3State *s,
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HostIOMMUDeviceIOMMUFD *idev,
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uint32_t *out_viommu_id,
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Error **errp);
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/**
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* @free_viommu: Optional callback. Free CMDQV viommu resources.
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* If NULL, the viommu_id is freed directly via iommufd_backend_free_id().
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*/
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void (*free_viommu)(SMMUv3State *s);
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/**
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* @get_type: Optional callback. Return the CMDQV implementation type.
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*/
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SMMUv3AccelCmdqvType (*get_type)(void);
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/**
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* @reset: Optional callback. Reset CMDQV state.
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*/
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void (*reset)(SMMUv3State *s);
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} SMMUv3AccelCmdqvOps;
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/*
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* Represents an accelerated SMMU instance backed by an iommufd vIOMMU object.
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* Holds bypass and abort proxy HWPT IDs used for device attachment.
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*/
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typedef struct SMMUv3AccelState {
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IOMMUFDViommu *viommu;
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IOMMUFDVeventq *veventq;
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uint32_t bypass_hwpt_id;
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uint32_t abort_hwpt_id;
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QLIST_HEAD(, SMMUv3AccelDevice) device_list;
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bool auto_mode;
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bool auto_finalised;
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const SMMUv3AccelCmdqvOps *cmdqv_ops;
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void *cmdqv; /* vendor specific CMDQV state */
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} SMMUv3AccelState;
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typedef struct SMMUS1Hwpt {
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uint32_t hwpt_id;
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} SMMUS1Hwpt;
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typedef struct SMMUv3AccelDevice {
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SMMUDevice sdev;
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HostIOMMUDeviceIOMMUFD *hiodi;
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SMMUS1Hwpt *s1_hwpt;
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IOMMUFDVdev *vdev;
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QLIST_ENTRY(SMMUv3AccelDevice) next;
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SMMUv3AccelState *s_accel;
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Error *unplug_blocker; /* set when CMDQV is active to block hot-unplug */
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} SMMUv3AccelDevice;
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bool smmuv3_accel_init(SMMUv3State *s, Error **errp);
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bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid,
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Error **errp);
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bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range,
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Error **errp);
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bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp);
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bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,
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Error **errp);
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void smmuv3_accel_idr_override(SMMUv3State *s);
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bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);
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int smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,
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void *buf, size_t size, Error **errp);
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void smmuv3_accel_reset(SMMUv3State *s);
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SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj);
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#endif /* HW_ARM_SMMUV3_ACCEL_H */
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