Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
422 lines
13 KiB
C
422 lines
13 KiB
C
/*
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* QEMU model of the Xilinx Zynq Double Data Rate Controller
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*
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* Copyright (c) Beckhoff Automation GmbH. & Co. KG
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/core/sysbus.h"
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#include "hw/core/register.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/core/registerfields.h"
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#include "system/block-backend.h"
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#include "system/address-spaces.h"
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#include "system/memory.h"
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#include "system/dma.h"
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#include "hw/misc/xlnx-zynq-ddrc.h"
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#include "migration/vmstate.h"
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#ifndef DDRCTRL_ERR_DEBUG
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#define DDRCTRL_ERR_DEBUG 0
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#endif
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static void zynq_ddrctrl_post_write(RegisterInfo *reg, uint64_t val)
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{
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DDRCTRLState *s = DDRCTRL(reg->opaque);
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if (reg->access->addr == A_DDRC_CTRL) {
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if (val & 0x1) {
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s->reg[R_MODE_STS_REG] |=
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(R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK & 0x1);
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} else {
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s->reg[R_MODE_STS_REG] &=
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~R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK;
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}
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}
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}
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static const RegisterAccessInfo xlnx_zynq_ddrc_regs_info[] = {
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/* 0x00 - 0x3C: Basic DDRC control and config */
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{ .name = "DDRC_CTRL",
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.addr = A_DDRC_CTRL,
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.reset = 0x00000200,
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.post_write = zynq_ddrctrl_post_write },
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{ .name = "TWO_RANK_CFG",
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.addr = A_TWO_RANK_CFG,
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.reset = 0x000C1076 },
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{ .name = "HPR_REG",
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.addr = A_HPR_REG,
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.reset = 0x03C0780F },
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{ .name = "LPR_REG",
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.addr = A_LPR_REG,
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.reset = 0x03C0780F },
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{ .name = "WR_REG",
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.addr = A_WR_REG,
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.reset = 0x0007F80F },
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{ .name = "DRAM_PARAM_REG0",
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.addr = A_DRAM_PARAM_REG0,
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.reset = 0x00041016 },
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{ .name = "DRAM_PARAM_REG1",
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.addr = A_DRAM_PARAM_REG1,
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.reset = 0x351B48D9 },
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{ .name = "DRAM_PARAM_REG2",
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.addr = A_DRAM_PARAM_REG2,
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.reset = 0x83015904 },
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{ .name = "DRAM_PARAM_REG3",
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.addr = A_DRAM_PARAM_REG3,
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.reset = 0x250882D0 },
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{ .name = "DRAM_PARAM_REG4",
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.addr = A_DRAM_PARAM_REG4,
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.reset = 0x0000003C },
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{ .name = "DRAM_INIT_PARAM",
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.addr = A_DRAM_INIT_PARAM,
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.reset = 0x00002007 },
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{ .name = "DRAM_EMR_REG",
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.addr = A_DRAM_EMR_REG,
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.reset = 0x00000008 },
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{ .name = "DRAM_EMR_MR_REG",
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.addr = A_DRAM_EMR_MR_REG,
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.reset = 0x00000940 },
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{ .name = "DRAM_BURST8_RDWR",
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.addr = A_DRAM_BURST8_RDWR,
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.reset = 0x00020034 },
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{ .name = "DRAM_DISABLE_DQ",
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.addr = A_DRAM_DISABLE_DQ },
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{ .name = "DRAM_ADDR_MAP_BANK",
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.addr = A_DRAM_ADDR_MAP_BANK,
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.reset = 0x00000F77 },
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{ .name = "DRAM_ADDR_MAP_COL",
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.addr = A_DRAM_ADDR_MAP_COL,
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.reset = 0xFFF00000 },
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{ .name = "DRAM_ADDR_MAP_ROW",
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.addr = A_DRAM_ADDR_MAP_ROW,
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.reset = 0x0FF55555 },
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{ .name = "DRAM_ODT_REG",
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.addr = A_DRAM_ODT_REG,
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.reset = 0x00000249 },
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/* 0x4C - 0x5C: PHY and DLL */
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{ .name = "PHY_DBG_REG",
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.addr = A_PHY_DBG_REG },
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{ .name = "PHY_CMD_TIMEOUT_RDDATA_CPT",
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.addr = A_PHY_CMD_TIMEOUT_RDDATA_CPT,
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.reset = 0x00010200 },
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{ .name = "MODE_STS_REG",
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.addr = A_MODE_STS_REG },
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{ .name = "DLL_CALIB",
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.addr = A_DLL_CALIB,
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.reset = 0x00000101 },
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{ .name = "ODT_DELAY_HOLD",
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.addr = A_ODT_DELAY_HOLD,
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.reset = 0x00000023 },
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/* 0x60 - 0x7C: Control registers */
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{ .name = "CTRL_REG1",
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.addr = A_CTRL_REG1,
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.reset = 0x0000003E },
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{ .name = "CTRL_REG2",
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.addr = A_CTRL_REG2,
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.reset = 0x00020000 },
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{ .name = "CTRL_REG3",
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.addr = A_CTRL_REG3,
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.reset = 0x00284027 },
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{ .name = "CTRL_REG4",
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.addr = A_CTRL_REG4,
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.reset = 0x00001610 },
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{ .name = "CTRL_REG5",
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.addr = A_CTRL_REG5,
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.reset = 0x00455111 },
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{ .name = "CTRL_REG6",
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.addr = A_CTRL_REG6,
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.reset = 0x00032222 },
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/* 0xA0 - 0xB4: Refresh, ZQ, powerdown, misc */
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{ .name = "CHE_REFRESH_TIMER0",
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.addr = A_CHE_REFRESH_TIMER0,
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.reset = 0x00008000 },
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{ .name = "CHE_T_ZQ",
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.addr = A_CHE_T_ZQ,
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.reset = 0x10300802 },
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{ .name = "CHE_T_ZQ_SHORT_INTERVAL_REG",
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.addr = A_CHE_T_ZQ_SHORT_INTERVAL_REG,
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.reset = 0x0020003A },
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{ .name = "DEEP_PWRDWN_REG",
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.addr = A_DEEP_PWRDWN_REG },
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{ .name = "REG_2C",
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.addr = A_REG_2C },
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{ .name = "REG_2D",
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.addr = A_REG_2D,
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.reset = 0x00000200 },
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/* 0xB8 - 0xF8: ECC, DFI, etc. */
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{ .name = "DFI_TIMING",
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.addr = A_DFI_TIMING,
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.reset = 0x00200067 },
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{ .name = "CHE_ECC_CONTROL_REG_OFFSET",
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.addr = A_CHE_ECC_CONTROL_REG_OFFSET },
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{ .name = "CHE_CORR_ECC_LOG_REG_OFFSET",
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.addr = A_CHE_CORR_ECC_LOG_REG_OFFSET },
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{ .name = "CHE_CORR_ECC_ADDR_REG_OFFSET",
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.addr = A_CHE_CORR_ECC_ADDR_REG_OFFSET },
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{ .name = "CHE_CORR_ECC_DATA_31_0_REG_OFFSET",
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.addr = A_CHE_CORR_ECC_DATA_31_0_REG_OFFSET },
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{ .name = "CHE_CORR_ECC_DATA_63_32_REG_OFFSET",
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.addr = A_CHE_CORR_ECC_DATA_63_32_REG_OFFSET },
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{ .name = "CHE_CORR_ECC_DATA_71_64_REG_OFFSET",
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.addr = A_CHE_CORR_ECC_DATA_71_64_REG_OFFSET },
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{ .name = "CHE_UNCORR_ECC_LOG_REG_OFFSET",
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.addr = A_CHE_UNCORR_ECC_LOG_REG_OFFSET },
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{ .name = "CHE_UNCORR_ECC_ADDR_REG_OFFSET",
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.addr = A_CHE_UNCORR_ECC_ADDR_REG_OFFSET },
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{ .name = "CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET",
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.addr = A_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET },
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{ .name = "CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET",
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.addr = A_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET },
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{ .name = "CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET",
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.addr = A_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET },
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{ .name = "CHE_ECC_STATS_REG_OFFSET",
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.addr = A_CHE_ECC_STATS_REG_OFFSET },
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{ .name = "ECC_SCRUB",
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.addr = A_ECC_SCRUB,
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.reset = 0x00000008 },
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{ .name = "CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET",
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.addr = A_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET },
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{ .name = "CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET",
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.addr = A_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET },
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/* 0x114 - 0x174: PHY config, ratios, DQS, WE */
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{ .name = "PHY_RCVER_ENABLE",
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.addr = A_PHY_RCVER_ENABLE },
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{ .name = "PHY_CONFIG0",
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.addr = A_PHY_CONFIG0,
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.reset = 0x40000001 },
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{ .name = "PHY_CONFIG1",
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.addr = A_PHY_CONFIG1,
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.reset = 0x40000001 },
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{ .name = "PHY_CONFIG2",
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.addr = A_PHY_CONFIG2,
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.reset = 0x40000001 },
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{ .name = "PHY_CONFIG3",
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.addr = A_PHY_CONFIG3,
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.reset = 0x40000001 },
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{ .name = "PHY_INIT_RATIO0",
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.addr = A_PHY_INIT_RATIO0 },
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{ .name = "PHY_INIT_RATIO1",
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.addr = A_PHY_INIT_RATIO1 },
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{ .name = "PHY_INIT_RATIO2",
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.addr = A_PHY_INIT_RATIO2 },
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{ .name = "PHY_INIT_RATIO3",
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.addr = A_PHY_INIT_RATIO3 },
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{ .name = "PHY_RD_DQS_CFG0",
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.addr = A_PHY_RD_DQS_CFG0,
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.reset = 0x00000040 },
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{ .name = "PHY_RD_DQS_CFG1",
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.addr = A_PHY_RD_DQS_CFG1,
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.reset = 0x00000040 },
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{ .name = "PHY_RD_DQS_CFG2",
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.addr = A_PHY_RD_DQS_CFG2,
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.reset = 0x00000040 },
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{ .name = "PHY_RD_DQS_CFG3",
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.addr = A_PHY_RD_DQS_CFG3,
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.reset = 0x00000040 },
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{ .name = "PHY_WR_DQS_CFG0",
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.addr = A_PHY_WR_DQS_CFG0 },
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{ .name = "PHY_WR_DQS_CFG1",
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.addr = A_PHY_WR_DQS_CFG1 },
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{ .name = "PHY_WR_DQS_CFG2",
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.addr = A_PHY_WR_DQS_CFG2 },
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{ .name = "PHY_WR_DQS_CFG3",
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.addr = A_PHY_WR_DQS_CFG3 },
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{ .name = "PHY_WE_CFG0",
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.addr = A_PHY_WE_CFG0,
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.reset = 0x00000040 },
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{ .name = "PHY_WE_CFG1",
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.addr = A_PHY_WE_CFG1,
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.reset = 0x00000040 },
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{ .name = "PHY_WE_CFG2",
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.addr = A_PHY_WE_CFG2,
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.reset = 0x00000040 },
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{ .name = "PHY_WE_CFG3",
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.addr = A_PHY_WE_CFG3,
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.reset = 0x00000040 },
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/* 0x17C - 0x194: Write data slaves, misc */
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{ .name = "WR_DATA_SLV0",
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.addr = A_WR_DATA_SLV0,
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.reset = 0x00000080 },
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{ .name = "WR_DATA_SLV1",
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.addr = A_WR_DATA_SLV1,
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.reset = 0x00000080 },
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{ .name = "WR_DATA_SLV2",
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.addr = A_WR_DATA_SLV2,
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.reset = 0x00000080 },
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{ .name = "WR_DATA_SLV3",
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.addr = A_WR_DATA_SLV3,
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.reset = 0x00000080 },
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{ .name = "REG_64",
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.addr = A_REG_64,
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.reset = 0x10020000 },
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{ .name = "REG_65",
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.addr = A_REG_65 },
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/* 0x1A4 - 0x1C4: Misc registers */
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{ .name = "REG69_6A0",
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.addr = A_REG69_6A0 },
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{ .name = "REG69_6A1",
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.addr = A_REG69_6A1 },
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{ .name = "REG6C_6D2",
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.addr = A_REG6C_6D2 },
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{ .name = "REG6C_6D3",
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.addr = A_REG6C_6D3 },
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{ .name = "REG6E_710",
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.addr = A_REG6E_710 },
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{ .name = "REG6E_711",
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.addr = A_REG6E_711 },
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{ .name = "REG6E_712",
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.addr = A_REG6E_712 },
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{ .name = "REG6E_713",
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.addr = A_REG6E_713 },
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/* 0x1CC - 0x1E8: DLL, PHY status */
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{ .name = "PHY_DLL_STS0",
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.addr = A_PHY_DLL_STS0 },
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{ .name = "PHY_DLL_STS1",
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.addr = A_PHY_DLL_STS1 },
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{ .name = "PHY_DLL_STS2",
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.addr = A_PHY_DLL_STS2 },
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{ .name = "PHY_DLL_STS3",
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.addr = A_PHY_DLL_STS3 },
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{ .name = "DLL_LOCK_STS",
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.addr = A_DLL_LOCK_STS },
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{ .name = "PHY_CTRL_STS",
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.addr = A_PHY_CTRL_STS },
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{ .name = "PHY_CTRL_STS_REG2",
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.addr = A_PHY_CTRL_STS_REG2 },
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/* 0x200 - 0x2B4: AXI, LPDDR, misc */
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{ .name = "AXI_ID",
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.addr = A_AXI_ID },
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{ .name = "PAGE_MASK",
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.addr = A_PAGE_MASK },
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{ .name = "AXI_PRIORITY_WR_PORT0",
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.addr = A_AXI_PRIORITY_WR_PORT0,
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.reset = 0x000803FF },
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{ .name = "AXI_PRIORITY_WR_PORT1",
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.addr = A_AXI_PRIORITY_WR_PORT1,
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.reset = 0x000803FF },
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{ .name = "AXI_PRIORITY_WR_PORT2",
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.addr = A_AXI_PRIORITY_WR_PORT2,
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.reset = 0x000803FF },
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{ .name = "AXI_PRIORITY_WR_PORT3",
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.addr = A_AXI_PRIORITY_WR_PORT3,
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.reset = 0x000803FF },
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{ .name = "AXI_PRIORITY_RD_PORT0",
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.addr = A_AXI_PRIORITY_RD_PORT0,
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.reset = 0x000003FF },
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{ .name = "AXI_PRIORITY_RD_PORT1",
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.addr = A_AXI_PRIORITY_RD_PORT1,
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.reset = 0x000003FF },
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{ .name = "AXI_PRIORITY_RD_PORT2",
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.addr = A_AXI_PRIORITY_RD_PORT2,
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.reset = 0x000003FF },
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{ .name = "AXI_PRIORITY_RD_PORT3",
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.addr = A_AXI_PRIORITY_RD_PORT3,
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.reset = 0x000003FF },
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{ .name = "EXCL_ACCESS_CFG0",
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.addr = A_EXCL_ACCESS_CFG0 },
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{ .name = "EXCL_ACCESS_CFG1",
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.addr = A_EXCL_ACCESS_CFG1 },
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{ .name = "EXCL_ACCESS_CFG2",
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.addr = A_EXCL_ACCESS_CFG2 },
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{ .name = "EXCL_ACCESS_CFG3",
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.addr = A_EXCL_ACCESS_CFG3 },
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{ .name = "MODE_REG_READ",
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.addr = A_MODE_REG_READ },
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{ .name = "LPDDR_CTRL0",
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.addr = A_LPDDR_CTRL0 },
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{ .name = "LPDDR_CTRL1",
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.addr = A_LPDDR_CTRL1 },
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{ .name = "LPDDR_CTRL2",
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.addr = A_LPDDR_CTRL2,
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.reset = 0x003C0015 },
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{ .name = "LPDDR_CTRL3",
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.addr = A_LPDDR_CTRL3,
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.reset = 0x00000601 },
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};
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static void zynq_ddrctrl_reset(DeviceState *dev)
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{
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DDRCTRLState *s = DDRCTRL(dev);
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int i;
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for (i = 0; i < ZYNQ_DDRCTRL_NUM_REG; ++i) {
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register_reset(&s->regs_info[i]);
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}
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}
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static const MemoryRegionOps ddrctrl_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const VMStateDescription vmstate_zynq_ddrctrl = {
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.name = "zynq_ddrc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg, DDRCTRLState, ZYNQ_DDRCTRL_NUM_REG),
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VMSTATE_END_OF_LIST()
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}
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};
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static void zynq_ddrctrl_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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DDRCTRLState *s = DDRCTRL(obj);
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s->reg_array =
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register_init_block32(DEVICE(obj), xlnx_zynq_ddrc_regs_info,
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ARRAY_SIZE(xlnx_zynq_ddrc_regs_info),
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s->regs_info, s->reg,
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&ddrctrl_ops,
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DDRCTRL_ERR_DEBUG,
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ZYNQ_DDRCTRL_MMIO_SIZE);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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}
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static void zynq_ddrctrl_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, zynq_ddrctrl_reset);
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dc->vmsd = &vmstate_zynq_ddrctrl;
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}
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static const TypeInfo ddrctrl_info = {
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.name = TYPE_DDRCTRL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(DDRCTRLState),
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.instance_init = zynq_ddrctrl_init,
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.class_init = zynq_ddrctrl_class_init,
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};
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static void ddrctrl_register_types(void)
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{
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type_register_static(&ddrctrl_info);
|
|
}
|
|
|
|
type_init(ddrctrl_register_types)
|