Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
34 lines
1.3 KiB
C
34 lines
1.3 KiB
C
/*
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* RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IOMMU_HPM_H
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#define HW_RISCV_IOMMU_HPM_H
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#include "qom/object.h"
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#include "hw/riscv/riscv-iommu.h"
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uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s);
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void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
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unsigned event_id);
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void riscv_iommu_hpm_timer_cb(void *priv);
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void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh);
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void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s);
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void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s, uint32_t evt_reg);
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#endif
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