Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
41 lines
1022 B
Python
Executable File
41 lines
1022 B
Python
Executable File
#!/usr/bin/env python3
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#
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# OpenSBI boot test for RISC-V machines
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#
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# Copyright (c) 2022, Ventana Micro
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#
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# This work is licensed under the terms of the GNU GPL, version 2 or
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# later. See the COPYING file in the top-level directory.
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from qemu_test import QemuSystemTest
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from qemu_test import wait_for_console_pattern
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class RiscvOpenSBI(QemuSystemTest):
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timeout = 5
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def boot_opensbi(self):
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self.vm.set_console()
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self.vm.launch()
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wait_for_console_pattern(self, 'Platform Name')
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wait_for_console_pattern(self, 'Boot HART MEDELEG')
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def test_riscv_spike(self):
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self.set_machine('spike')
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self.boot_opensbi()
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def test_riscv_sifive_u(self):
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self.set_machine('sifive_u')
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self.boot_opensbi()
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def test_riscv_tt_atlantis(self):
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self.set_machine('tt-atlantis')
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self.boot_opensbi()
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def test_riscv_virt(self):
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self.set_machine('virt')
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self.boot_opensbi()
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if __name__ == '__main__':
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QemuSystemTest.main()
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