Yaya48
cf256aa081
Upstream: https://gitlab.com/qemu-project/qemu.git Upstream-Commit: d2e570cc0f97b936902a5b1b86b73c0f5998b475
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/*
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* PowerNV XSCOM Bus
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PNV_XSCOM_H
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#define PNV_XSCOM_H
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#define SMT 4 /* some tests will break if less than 4 */
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typedef enum PnvChipType {
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PNV_CHIP_POWER8, /* AKA Venice */
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PNV_CHIP_POWER9, /* AKA Nimbus */
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PNV_CHIP_POWER10,
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PNV_CHIP_POWER11,
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} PnvChipType;
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typedef struct PnvChip {
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PnvChipType chip_type;
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const char *cpu_model;
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uint64_t xscom_base;
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uint64_t cfam_id;
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uint32_t first_core;
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uint32_t num_i2c;
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} PnvChip;
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static const PnvChip pnv_chips[] = {
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{
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.chip_type = PNV_CHIP_POWER8,
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.cpu_model = "POWER8",
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.xscom_base = 0x0003fc0000000000ull,
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.cfam_id = 0x220ea04980000000ull,
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.first_core = 0x1,
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.num_i2c = 0,
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},
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{
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.chip_type = PNV_CHIP_POWER9,
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.cpu_model = "POWER9",
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.xscom_base = 0x000603fc00000000ull,
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.cfam_id = 0x220d104900008000ull,
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.first_core = 0x0,
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.num_i2c = 4,
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},
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{
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.chip_type = PNV_CHIP_POWER10,
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.cpu_model = "POWER10",
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.xscom_base = 0x000603fc00000000ull,
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.cfam_id = 0x220da04980000000ull,
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.first_core = 0x0,
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.num_i2c = 4,
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},
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{
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.chip_type = PNV_CHIP_POWER11,
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.cpu_model = "Power11",
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.xscom_base = 0x000603fc00000000ull,
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.cfam_id = 0x220da04980000000ull,
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.first_core = 0x0,
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.num_i2c = 0,
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},
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};
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static inline uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
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{
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uint64_t addr = chip->xscom_base;
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if ((chip->chip_type == PNV_CHIP_POWER11) ||
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(chip->chip_type == PNV_CHIP_POWER10) ||
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(chip->chip_type == PNV_CHIP_POWER9)) {
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addr |= ((uint64_t) pcba << 3);
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} else {
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addr |= (((uint64_t) pcba << 4) & ~0xffull) |
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(((uint64_t) pcba << 3) & 0x78);
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}
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return addr;
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}
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static const char *pnv_get_machine_type(enum PnvChipType chip_type)
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{
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static const char *const machine_types[] = {
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[PNV_CHIP_POWER8] = "powernv8",
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[PNV_CHIP_POWER9] = "powernv9",
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[PNV_CHIP_POWER10] = "powernv10",
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[PNV_CHIP_POWER11] = "powernv11",
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};
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g_assert(chip_type <= PNV_CHIP_POWER11);
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return machine_types[chip_type];
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}
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#endif /* PNV_XSCOM_H */
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