IOS LLE: execute ARMv5TE enhanced DSP instructions (StarletOS phase 11 I1)
SMLAxy, SMLAWy, SMULWy, SMLALxy, SMULxy, QADD, QSUB, QDADD and QDSUB were decoded as compare data processing that writes no register; the ARM926EJ-S implements them. The interpreter now executes them with the Q flag and the JIT leaves them to it. Adds ARMv5TEEnhancedDSPInstructions. Co-Authored-By: Claude Opus 5.5 <[email protected]>
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@@ -53,18 +53,18 @@
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMCore.cpp",
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"sha256": "262946f1fb95250d1aa1ca73c9bc27ef5f83511731bf84c765a41b04fe7ff70a",
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"bytes": 76503
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"sha256": "2559d69e1ec654734f788312cf5f3dca4de63e22e0880626306e8d15a4585648",
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"bytes": 80026
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMCore.h",
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"sha256": "fa80b0d697e19f0aee178be4b13097ad5466f0bbd0cb9b3e7a74876c045b731f",
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"bytes": 14647
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"sha256": "c3263bebbbdb7cd1119cc74ad328a63ad969136c1755ccf8e06e6549f23da3aa",
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"bytes": 14758
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMJitX64.cpp",
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"sha256": "30ac3e6f74edd40a76406394ed40d66a1ca5b6b9a17b9699a1534d255320108f",
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"bytes": 109425
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"sha256": "724382f4f66442d51382d3249bea68620d7417a6c7f48b0c19efa60e942a183c",
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"bytes": 109615
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},
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{
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"path": "Source/Core/Core/IOS/Starlet/ARMJitX64.h",
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@@ -189,6 +189,15 @@
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"Source/Core/Core/IOS/Starlet/StarletMemory.cpp",
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"Source/Core/Core/IOS/Starlet/StarletMemory.h"
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]
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},
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{
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"recordedAt": "2026-10-06",
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"purpose": "StarletOS Phase 11 proposal I1: the ARM interpreter executes the ARMv5TE enhanced DSP instructions (SMLAxy, SMLAWy, SMULWy, SMLALxy, SMULxy, QADD, QSUB, QDADD, QDSUB, Q flag), previously decoded as compare data processing that wrote no register; the JIT leaves them to the interpreter; test ARMv5TEEnhancedDSPInstructions",
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"files": [
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"Source/Core/Core/IOS/Starlet/ARMCore.cpp",
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"Source/Core/Core/IOS/Starlet/ARMCore.h",
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"Source/Core/Core/IOS/Starlet/ARMJitX64.cpp"
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]
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}
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]
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}
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