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Author SHA1 Message Date
Fiora 0e34737390 Merge pull request #2121 from JosJuice/remove-sudtr-note 
Remove "Needed for a few games." from fast disc speed description
 2015-02-24 13:12:48 -08:00
Fiora c54a8c54fb Merge pull request #1994 from Tilka/vtune 
JitRegister: fix VTune integration
 2015-02-22 07:58:12 -08:00
Fiora 8cd32e171a Merge pull request #2095 from lioncash/correctness 
Interpreter: Set the FPCC bits correctly for ordered/unordered compares.
 2015-02-22 07:53:52 -08:00
Fiora 7d9c9ae177 Merge pull request #1750 from Buddybenj/license 
Use Consistent Spelling of "License"
 2015-02-20 00:22:22 -08:00
Fiora 53bf21e15a Merge pull request #2066 from lpereira/regcache-with-variadic-tpl 
Jit64: Use variadic templates for RegCache locking
 2015-02-17 08:53:07 -08:00
Fiora 9761df422a Merge pull request #2043 from Tilka/fix_jump 
Jit64: turn short jmp into near jmp
 2015-02-13 01:08:57 -08:00
Fiora 451c4f3c4b Merge pull request #1969 from JosJuice/dvd-decryption-optimization 
VolumeWiiCrypted: Decryption optimization
 2015-02-08 11:57:55 -08:00
Fiora 93c9eab8e5 Merge pull request #2008 from mrgreywater/master 
Add COUNTRY_GERMANY to load german disks without warning
 2015-02-08 11:55:45 -08:00
Fiora 73d65f3ad3 Merge pull request #1874 from magumagu/remove-unchecked-reads 
JIT: cleanup instrction merging for idle loop and dcbst.
 2015-02-07 13:48:22 -08:00
Fiora d5e342f229 JIT: fix regression in non-fastmem for psq_st 2015-01-11 11:20:58 -08:00
Fiora e8cfcd3aeb JIT: make instruction merging generic 
Now it should be easier to merge more than 2-instruction-long sequences.
Also correct some minor inconsistencies in behavior between instruction
merging cases.
 2015-01-11 09:11:18 -08:00
Fiora 5b825e9091 StringUtils: use C locale instead of .1252 
Fixes regression on Linux.
 2015-01-11 00:15:57 -08:00
Fiora 8237004448 JIT: optimize for the common case of unquantized psq_l/st 
Optimistically assume used GQRs are 0 in blocks that only use one GQR, and
bail at the start of the block and recompile if that assumption fails.

Many games use almost entirely unquantized stores (e.g. Rebel Strike, Sonic
Colors), so this will likely be a big performance improvement across the board
for games with heavy use of paired singles.
 2015-01-10 14:14:43 -08:00
Fiora c2c950108d Support overclocking and underclocking the Gamecube CPU 
Won't work with all games, but provides a nice way to spend extra CPU to make
a variable framerate game faster (e.g. Spyro or The Last Story), or to make
a game use less CPU at the cost of a lower framerate (e.g. Rogue Leader).
 2015-01-10 10:46:38 -08:00
Fiora 55b509b739 Interpreter: fix slwx 2015-01-09 11:39:41 -08:00
Fiora 8f7c799794 JIT: catch illegal instruction errors 
Still crash, but at least give a message informing the world that it happened.
 2015-01-06 11:06:49 -08:00
Fiora e85f0ff179 MMU: fix problems with blocks that cross vmem page boundaries 
In rare cases, this can result in a violation of the JIT block cache constraint
that blocks must end in the same place. This can cause instability, lockups,
due to blocks not properly being invalidated properly.
l Please enter the commit message for your changes. Lines starting
 2015-01-05 10:46:04 -08:00
Fiora b058bbd223 JIT: move mfcr code to JitAsmCommon 
It's like 80+ instructions, so inlining it on every use of mfcr is probably
not the best for the icache.
 2015-01-05 10:46:03 -08:00
Fiora 821db9798c Memmap: clean up function argument names. 
To be more consistent overall.
 2015-01-05 10:46:02 -08:00
Fiora 3d2492627f Fastmem: increase the size of trampoline cache in MMU mode, check space 
Fastmem in MMU mode generates way more trampolines than normal, so we need
a bunch more space too, lest we run out of room.
 2015-01-05 10:46:01 -08:00
Fiora 1ee83e332e MMU: optimize PTE lookup code 
Pull out calculation of PTE1 instead of comparing the separate parts.
 2015-01-05 10:46:01 -08:00
Fiora 16e756cb39 MMU: fix TLB behavior on setting C bit 
We shouldn't be updating the TLB when setting the C bit.

Bug reported by tueidj.
 2015-01-05 10:45:59 -08:00
Fiora 8903df7300 MMU: simplify code to restore original data register after failed load 
Instead of passing the value around constantly, just store it in the regcache,
note where it is, and restore it on the exception path.

This saves a whole bunch of pushing and popping and gives a ~5% speed boost
in Rebel Strike. It's a bit ugly, but it simplifies a lot of code and is
faster, too.
 2015-01-05 10:45:59 -08:00
Fiora 53b44ccb3a x64ABI: enhance MOVTwo to take an offset 
This lets us merge displacements into MOVTwo in trampolines.
 2015-01-05 10:45:58 -08:00
Fiora 2a8936312e Fastmem: jump to trampolines instead of calling them 
Should be slightly faster, and also lets us skip the nops on the way back.

Remove the trampoline cache, since it isn't really useful anymore with this.
 2015-01-05 10:45:54 -08:00
Fiora 9923d705df JIT: simplify and optimize memcheck macros 
Instead of jumping over update code and similar, just jump directly to the
handler.

This avoids redundant exception checks in the case where we can't do fastmem
memory operations (e.g. paired loadstore).
 2015-01-05 10:34:59 -08:00
Fiora 6dc7cf29f3 JIT: implement crset special case 
Rebel Strike seems to use this one.
 2015-01-05 10:34:59 -08:00
Fiora 0ff6ad5734 MMU: handle exception checks in fastmem 
Inspired by a patch by magumagu.
 2015-01-05 10:34:58 -08:00
Fiora 190312e1a6 MMU: enable fastmem stores 2015-01-05 10:34:58 -08:00
Fiora 8e1c92f2e7 MMU: remove goto in MMU fast past check 
Split into a separate patch to avoid rebasing conflicts and to split from
functional changes.
 2015-01-05 10:34:57 -08:00
Fiora 6f028257d7 MMU: remove code that looks totally wrong 
I don't think this affects any games (who puts PTEs in MEM2?) but it didn't
make any sense.
 2015-01-05 10:34:57 -08:00
Fiora dde8b24d00 MMU: small simplification of TLB structure 
We only need one "recent" per set, not NUM_WAYS recents. Slightly faster.
Breaks savestate compatibility.
 2015-01-05 10:34:56 -08:00
Fiora a0e5c76a1f Memmapfunctions: more refactoring and optimizations 
Try to clean up some redundant code, simplify a few checks, and simplify
page accesses.
 2015-01-05 10:34:56 -08:00
Fiora c2ed29fe0d MemmapFunctions: various MMU optimizations 
Small TLB lookup optimizations: this is the hot path for MMU code, so try to
make it better.

Template the TLB lookup functions based on the lookup type (opcode, data,
no exception).

Clean up the Read/Write functions and make them more consistent.

Add an early-exit path for MMU accesses to ReadFromHardware/WriteToHardware.
 2015-01-05 10:34:55 -08:00
Fiora ea23ce2726 MMU: fix rollback in DSIs on page-crossing stores 
I don't know if this affected anything, but it was subtly wrong.
Also reorganize the loads to match, for consistency.
 2015-01-05 10:34:55 -08:00
Fiora 8a6ea918b6 GekkoDisassembler: fix display of CRs in branch operations 2015-01-03 19:53:55 -08:00
Fiora 33b03fab81 JIT: cleanups/optimizations for ps loadstore 
I'm not quite sure why the float paired stores were written how they were,
but it should be more consistent now.

Also get rid of the use of a psTemp global that wasn't really needed.

Add some comments.
 2015-01-03 10:30:13 -08:00
Fiora 92a0716f65 Memory: forceinline read/write hardware functions, TLB/page functions 
MSVC wasn't actually inlining these. Should give a nontrivial performance boost
in MMU-heavy games.
 2014-12-30 18:04:21 -08:00
Fiora 354e255827 JIT: fix carry optimization on blocks that end early 
I don't know if this shows up currently, but e.g. if you force blocks to be
under a certain length, this problem (a crash) shows up.
 2014-12-27 23:20:05 -08:00
Fiora e7a49ae5f3 Eliminate some spammy log messages in MMU mode 
dcbz: just don't use GetPointer, that can't be right anyways
ppcanalyst: don't print "instruction hex 0" messages in MMU mode, where ISIs
are expected.
 2014-12-21 12:41:44 -08:00
Fiora 3b7d7da1ac JIT: Fix redundant MOVs in x86 trampolines 
Fixes spammy log messages about redundant MOVs.
 2014-12-21 12:06:07 -08:00
Fiora 76ca42b758 JIT: free up a register by eliminating RCODE_POINTERS 
Also use shorter code in the dispatcher if we can get away with it (e.g. on
Windows where the relevant memory is in the low 2GB).
 2014-12-14 18:19:37 -08:00
Fiora 3effd08843 FIFO: allocate slightly more for SIMD vertex loader overreads 
May fix crashes in rare cases.
 2014-12-10 05:52:55 -08:00
Fiora 92aad1140e JIT: fix MOVD_xmm typoes in ConvertDoubleToSingle 
Ordering, plus MOVQ instead of MOVD
 2014-12-09 04:19:44 -08:00
Fiora 68972da1e5 JIT: fix possible panicalert in loadstore 
Didn't bind address register tcorrectly in a very rare case.
 2014-12-06 16:09:13 -08:00
Fiora 3d12849967 JIT: fix snan/qnan handling in float loads/stores 
Also simplify the conversion code with some suggestions by flacs; might even
be slightly faster now despite handling more cases.
 2014-12-06 13:07:24 -08:00
Fiora e3578683e3 Vertex loader: optimize texmtx_write_float4 
Seems to be pretty high in the profile in some geometry-heavy games like The
Last Story, and the compiler-generated assembly is terrifyingly bad, so
SSE-ize it.
 2014-12-03 11:17:05 -08:00
Fiora a4c6cf85e9 TLB: fix backwards exception check 2014-12-03 06:00:23 -08:00
Fiora 863fb91cad JIT: fix profiler call 
Sometimes this seems to require a 64-bit offset, so use CallFunction instead
 2014-12-02 10:17:58 -08:00
Fiora 644a661bf1 JIT: remove unnecessary pxor in paired stores 
I don't think this is necessary anymore?
 2014-11-30 08:11:45 -08:00
Fiora 72c96c20d3 JIT: more optimizing of float ops based on known input characteristics 
If the inputs are both float singles, and the top half is known to be identical
to the bottom half, we can use packed arithmetic instead of scalar to skip
the movddup.

This is slower on a few rather old CPUs, plus the Atom+Silvermont, so detect
Atom and disable it in that case.

Also avoid PPC_FP on stores if we know that the output came from a float op.
 2014-11-29 11:33:11 -08:00
Fiora 4e0591cdf1 JIT: float instruction attribute fixes, fix binding mistakes 
These instructions modify only the bottom halves of the output register,
so the output register needs to be treated as an input too.
 2014-11-29 11:30:52 -08:00
Fiora 8d039a77af JIT: minor cleanup, avoid MOVSD where MOVAPD will do 
Avoids false dependencies.
 2014-11-29 11:30:51 -08:00
Fiora 7df50b0710 JIT: skip weird fmul rounding if the input is known to be single precision 2014-11-29 11:30:51 -08:00
Fiora 7acd5eba17 Vertex loader: use ABI_CallFunction 
Should result in faster/shorter code sequences on platforms where generated
code is close enough to the code segment (e.g. Windows).
 2014-11-28 20:26:00 -08:00
Fiora d42305aba0 JIT: fix fcmp+cror merging bug 
Destination CR bit needs to be cleared if it's not one of the sources.
 2014-11-28 16:11:04 -08:00
Fiora 41f5ef3304 JIT: remove "fast interrupts" option set and then used nowhere 2014-11-28 06:42:40 -08:00
Fiora 3e893913dd JIT: fix Force25BitPrecision with accurate single precision mode off 
Doesn't affect anything now, but it's more correct (and should make setting
AccurateSinglePrecision to false work properly now).
 2014-11-28 06:39:47 -08:00
Fiora 561e96b080 JIT: clear FIFO write addresses when block cache is cleared 
Fixes a spurious FIFO write check which caused a flags locking assert in
Splinter Cell: Double Agent.
 2014-11-27 17:15:01 -08:00
Fiora 3be31ca2c8 JIT: remove "accurate fcmp" option 
This doesn't seem to be necessary anymore now that FPRF is implemented in the
JIT. Technically, this isn't the same as before, since the JIT doesn't
implement the fcmp exception semantics, but as far as testing has shown, this
doesn't seem necessary.

This should make games that use FPRF a few percent faster (e.g. F-Zero GX)
since fcmpx no longer has to be fallbacked.
 2014-11-25 09:54:40 -08:00
Fiora 3ddf82a318 Vertex Loader: SSE implementations of more position/texcoord/normal formats 
~35-45% faster NFS:HP2, possibly other vertex-bound games.
 2014-11-20 02:13:19 -08:00
Fiora 733795891c D3D: fix issues with multi-level 1x1 textures on D3D 
Fixes NBA 2K11, maybe other things.
 2014-11-12 21:43:48 -08:00
Fiora 4b105ed0e4 JIT: revert accuracy improvement to mftb 
Fixes a few games (e.g. Karaoke Revolution Party) for reasons explained in the
comments.
 2014-11-10 20:31:07 -08:00
Fiora 6603f98d04 JIT: add 64-bit write support to FIFO functions 
Also fix 64-bit values passed to CallAC and otherwise correct immediate
handling in FIFO writes.
Fixes 007 Nightfire.
 2014-11-09 21:24:30 -08:00
Fiora b8d88a41e0 JIT: remove accidentally left-in debug code 2014-11-05 17:44:13 -08:00
Fiora b81686b582 JIT: fix register preloading 
Partially broken by typoes in the bitset patch.
 2014-11-04 04:50:05 -08:00
Fiora f8880c0284 JIT: fix typo in optimization patch 
Whoops... made us flush everything on every branch.
 2014-11-04 02:04:30 -08:00
Fiora 768273f59b JIT: revert cmpXX optimization 
It seems like this wasn't correct in 100% of cases.
 2014-11-03 17:50:20 -08:00
Fiora ce71c3cd4e JIT: fix valid_block marking 
This caused invalidations that only affected the last portion of a JIT block
to fail, breaking Wii64's block linking. It might affect a bunch of other
games too; I haven't tested.
 2014-11-03 16:23:44 -08:00
Fiora fc63c7ecae JIT: genericize immediate address handling, support in float stores too 2014-11-03 01:31:39 -08:00
Fiora e729fc4a28 JIT: fix dumb mistake in crclr optimization patch 2014-11-02 21:03:11 -08:00
Fiora 7deaf00c44 JIT: more mftb fixes 
A very subtle difference in how I calculated the timebase value seems
to have broken Karaoke Revolution; this seems to fix it. Also be a bit more
paranoid in conditions for mftb merging.
 2014-11-01 03:15:25 -07:00
Fiora fb0960f0ee JIT: flush unused registers during branch merges 
Also correct some flags in interpreter tables.
 2014-10-29 00:32:59 -07:00
Fiora 1ec1a9c33a JIT: optimize crclr special case of crxor 2014-10-29 00:30:27 -07:00
Fiora 97fba41860 JIT: merge fcmpx and cror 
Almost all uses of boolean condition-register ops in real code seem to be
the combination fcmpx + cror (e.g. for <= or >=). This merges the two.
 2014-10-29 00:30:27 -07:00
Fiora a666bb6bf6 JIT: optimize mulhwu 2014-10-29 00:30:26 -07:00
Fiora 5b5e462200 JIT: reorder blr comparisons 
This should allow macro-op fusion in blr instructions.
 2014-10-29 00:30:26 -07:00
Fiora 7388c62439 JIT: use BLR optimization to avoid anding LR with 0xFFFFFFFC 
Should save roughly one instruction per blr.
 2014-10-29 00:30:26 -07:00
Fiora cec2cb9d38 JIT: micro-optimize cmpXX a bit more for lower latency/code size 2014-10-29 00:30:25 -07:00
Fiora f4fa8d0b83 MMU: allow page-table loads/stores if MMU is off 
Fixes regressions in some games that apparently required this to work, but
don't really require full MMU emulation (e.g. with exceptions and all).
 2014-10-21 05:55:56 -07:00
Fiora d7ff482618 Fix FPRF flag setting 
Looks like I didn't quite change every place it needed to be renamed.
 2014-10-21 04:56:35 -07:00
Fiora d2e004fa9e Use CRC to output 64 bits instead of 32 
A bit hacky, but should dramatically reduce the odds of hash collision.
 2014-10-18 00:24:35 -07:00
Fiora c74b4df13e Add FPRF interface option, change from EnableFPRF to just FPRF 2014-10-17 19:06:18 -07:00
Fiora 719326df65 Make EnableBATs an option instead of disabling it entirely 2014-10-17 19:05:01 -07:00
Fiora 99169eb620 JIT: fix profiler on non-Windows OSs 
Still doesn't support timing code (since that's Windows-only), but run counts
will at least work without crashing.
 2014-10-17 16:48:09 -07:00
Fiora 15a4bccb73 Hash: unroll CRC loop, since CRC32 typically has nontrivial latency 
Seems to be about 20-30% faster texture cache hashing on my machine.
 2014-10-17 15:39:08 -07:00
Fiora 6ac2fcca61 MMU: disable BAT resolution 
No known games, not even Wii MMU games like Cars 2 and Toy Story 3, use custom
BATs. This makes BAT resolution a waste of time. BAT handling could be
optimized significantly, but as long as nothing uses it, it's easier to just
disable it.

Should significantly improve performance in MMU-heavy games.
 2014-10-13 22:04:03 -07:00
Fiora 7ba9a8537b JIT: add basic register allocation heuristics 
Should be at least a bit better than the previous LRU approach. Currently
has two basic components: whether a register is dirty (dirty registers need
to be stored, so clobbering them hurts more) and how many other registers will
be used between now and the next time a register gets used.

Also don't pre-load values that don't need to be in registers.
 2014-10-09 20:09:14 -07:00
Fiora 9d45f51459 JIT: fix accidental disabling of block linking by default 
Oops.
 2014-10-09 12:00:40 -07:00
Fiora 8bf2cf0641 Debug: fix disable block linking option 
Previously it did the opposite of what it was supposed to; when checked, it'd
turn block linking on, and when unchecked, it'd turn it off.

Also update JITIL's block linking disabling in debug mode to match the behavior
of the regular JIT.
 2014-10-08 19:03:25 -07:00
Fiora 75a1310ba9 CPU: improve instruction table flags for RC bits 2014-10-08 11:44:37 -07:00
Fiora 9734f0c834 JIT64: use FMA instructions 2014-10-07 21:41:01 -07:00
Fiora 4289221584 X64Emitter: add unit test for FMA 2014-10-07 18:21:07 -07:00
Fiora 019657cd93 X64Emitter: add FMA3 support 2014-10-07 18:21:07 -07:00
Fiora 5919d0962f JIT: re-add profiling support on x86_64 
Still gives rather inaccurate results with conditional continue and/or
branch merging on, so those should probably be turned off when using it.
 2014-10-06 20:26:58 -07:00
Fiora 9b29fe8aed WIP: don't let the backpatcher hit the same location twice 
If a location is hit by the backpatcher, don't fastmem it when recompiling the
block unless the block has actually been invalidated.
 2014-10-04 21:28:21 -07:00
Fiora 17c56b58ab JIT: set clear_cache_asap to false when clearing the cache 
Would probably result in continual cache-clearing if the stack overflow code
in the BLR optimizations triggers.
 2014-10-03 20:08:27 -07:00
Fiora bf014636c8 JIT: add more AVX support, reduce redundant XMM moves 
10-20% reduction in typical compiled block size for float-heavy JIT blocks.
 2014-10-03 16:17:08 -07:00
Fiora 8fe730194b JIT: load registers if they're going to be used later in the block 2014-10-03 11:58:04 -07:00
Fiora 6bff99fa75 JitAsmCommon: remove a few redundant moves 2014-10-03 10:05:42 -07:00