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Author SHA1 Message Date
Fiora 190312e1a6 MMU: enable fastmem stores 2015-01-05 10:34:58 -08:00
Fiora 8e1c92f2e7 MMU: remove goto in MMU fast past check 
Split into a separate patch to avoid rebasing conflicts and to split from
functional changes.
 2015-01-05 10:34:57 -08:00
Fiora 6f028257d7 MMU: remove code that looks totally wrong 
I don't think this affects any games (who puts PTEs in MEM2?) but it didn't
make any sense.
 2015-01-05 10:34:57 -08:00
Fiora dde8b24d00 MMU: small simplification of TLB structure 
We only need one "recent" per set, not NUM_WAYS recents. Slightly faster.
Breaks savestate compatibility.
 2015-01-05 10:34:56 -08:00
Fiora a0e5c76a1f Memmapfunctions: more refactoring and optimizations 
Try to clean up some redundant code, simplify a few checks, and simplify
page accesses.
 2015-01-05 10:34:56 -08:00
Fiora c2ed29fe0d MemmapFunctions: various MMU optimizations 
Small TLB lookup optimizations: this is the hot path for MMU code, so try to
make it better.

Template the TLB lookup functions based on the lookup type (opcode, data,
no exception).

Clean up the Read/Write functions and make them more consistent.

Add an early-exit path for MMU accesses to ReadFromHardware/WriteToHardware.
 2015-01-05 10:34:55 -08:00
Fiora ea23ce2726 MMU: fix rollback in DSIs on page-crossing stores 
I don't know if this affected anything, but it was subtly wrong.
Also reorganize the loads to match, for consistency.
 2015-01-05 10:34:55 -08:00
Fiora 8a6ea918b6 GekkoDisassembler: fix display of CRs in branch operations 2015-01-03 19:53:55 -08:00
Fiora 92a0716f65 Memory: forceinline read/write hardware functions, TLB/page functions 
MSVC wasn't actually inlining these. Should give a nontrivial performance boost
in MMU-heavy games.
 2014-12-30 18:04:21 -08:00
Fiora 354e255827 JIT: fix carry optimization on blocks that end early 
I don't know if this shows up currently, but e.g. if you force blocks to be
under a certain length, this problem (a crash) shows up.
 2014-12-27 23:20:05 -08:00
Fiora e7a49ae5f3 Eliminate some spammy log messages in MMU mode 
dcbz: just don't use GetPointer, that can't be right anyways
ppcanalyst: don't print "instruction hex 0" messages in MMU mode, where ISIs
are expected.
 2014-12-21 12:41:44 -08:00
Fiora 3b7d7da1ac JIT: Fix redundant MOVs in x86 trampolines 
Fixes spammy log messages about redundant MOVs.
 2014-12-21 12:06:07 -08:00
Fiora 76ca42b758 JIT: free up a register by eliminating RCODE_POINTERS 
Also use shorter code in the dispatcher if we can get away with it (e.g. on
Windows where the relevant memory is in the low 2GB).
 2014-12-14 18:19:37 -08:00
Fiora 3effd08843 FIFO: allocate slightly more for SIMD vertex loader overreads 
May fix crashes in rare cases.
 2014-12-10 05:52:55 -08:00
Fiora 92aad1140e JIT: fix MOVD_xmm typoes in ConvertDoubleToSingle 
Ordering, plus MOVQ instead of MOVD
 2014-12-09 04:19:44 -08:00
Fiora 68972da1e5 JIT: fix possible panicalert in loadstore 
Didn't bind address register tcorrectly in a very rare case.
 2014-12-06 16:09:13 -08:00
Fiora 3d12849967 JIT: fix snan/qnan handling in float loads/stores 
Also simplify the conversion code with some suggestions by flacs; might even
be slightly faster now despite handling more cases.
 2014-12-06 13:07:24 -08:00
Fiora e3578683e3 Vertex loader: optimize texmtx_write_float4 
Seems to be pretty high in the profile in some geometry-heavy games like The
Last Story, and the compiler-generated assembly is terrifyingly bad, so
SSE-ize it.
 2014-12-03 11:17:05 -08:00
Fiora a4c6cf85e9 TLB: fix backwards exception check 2014-12-03 06:00:23 -08:00
Fiora 863fb91cad JIT: fix profiler call 
Sometimes this seems to require a 64-bit offset, so use CallFunction instead
 2014-12-02 10:17:58 -08:00
Fiora 644a661bf1 JIT: remove unnecessary pxor in paired stores 
I don't think this is necessary anymore?
 2014-11-30 08:11:45 -08:00
Fiora 72c96c20d3 JIT: more optimizing of float ops based on known input characteristics 
If the inputs are both float singles, and the top half is known to be identical
to the bottom half, we can use packed arithmetic instead of scalar to skip
the movddup.

This is slower on a few rather old CPUs, plus the Atom+Silvermont, so detect
Atom and disable it in that case.

Also avoid PPC_FP on stores if we know that the output came from a float op.
 2014-11-29 11:33:11 -08:00
Fiora 4e0591cdf1 JIT: float instruction attribute fixes, fix binding mistakes 
These instructions modify only the bottom halves of the output register,
so the output register needs to be treated as an input too.
 2014-11-29 11:30:52 -08:00
Fiora 8d039a77af JIT: minor cleanup, avoid MOVSD where MOVAPD will do 
Avoids false dependencies.
 2014-11-29 11:30:51 -08:00
Fiora 7df50b0710 JIT: skip weird fmul rounding if the input is known to be single precision 2014-11-29 11:30:51 -08:00
Fiora 7acd5eba17 Vertex loader: use ABI_CallFunction 
Should result in faster/shorter code sequences on platforms where generated
code is close enough to the code segment (e.g. Windows).
 2014-11-28 20:26:00 -08:00
Fiora d42305aba0 JIT: fix fcmp+cror merging bug 
Destination CR bit needs to be cleared if it's not one of the sources.
 2014-11-28 16:11:04 -08:00
Fiora 41f5ef3304 JIT: remove "fast interrupts" option set and then used nowhere 2014-11-28 06:42:40 -08:00
Fiora 3e893913dd JIT: fix Force25BitPrecision with accurate single precision mode off 
Doesn't affect anything now, but it's more correct (and should make setting
AccurateSinglePrecision to false work properly now).
 2014-11-28 06:39:47 -08:00
Fiora 561e96b080 JIT: clear FIFO write addresses when block cache is cleared 
Fixes a spurious FIFO write check which caused a flags locking assert in
Splinter Cell: Double Agent.
 2014-11-27 17:15:01 -08:00
Fiora 3be31ca2c8 JIT: remove "accurate fcmp" option 
This doesn't seem to be necessary anymore now that FPRF is implemented in the
JIT. Technically, this isn't the same as before, since the JIT doesn't
implement the fcmp exception semantics, but as far as testing has shown, this
doesn't seem necessary.

This should make games that use FPRF a few percent faster (e.g. F-Zero GX)
since fcmpx no longer has to be fallbacked.
 2014-11-25 09:54:40 -08:00
Fiora 3ddf82a318 Vertex Loader: SSE implementations of more position/texcoord/normal formats 
~35-45% faster NFS:HP2, possibly other vertex-bound games.
 2014-11-20 02:13:19 -08:00
Fiora 733795891c D3D: fix issues with multi-level 1x1 textures on D3D 
Fixes NBA 2K11, maybe other things.
 2014-11-12 21:43:48 -08:00
Fiora 4b105ed0e4 JIT: revert accuracy improvement to mftb 
Fixes a few games (e.g. Karaoke Revolution Party) for reasons explained in the
comments.
 2014-11-10 20:31:07 -08:00
Fiora 6603f98d04 JIT: add 64-bit write support to FIFO functions 
Also fix 64-bit values passed to CallAC and otherwise correct immediate
handling in FIFO writes.
Fixes 007 Nightfire.
 2014-11-09 21:24:30 -08:00
Fiora b8d88a41e0 JIT: remove accidentally left-in debug code 2014-11-05 17:44:13 -08:00
Fiora b81686b582 JIT: fix register preloading 
Partially broken by typoes in the bitset patch.
 2014-11-04 04:50:05 -08:00
Fiora f8880c0284 JIT: fix typo in optimization patch 
Whoops... made us flush everything on every branch.
 2014-11-04 02:04:30 -08:00
Fiora 768273f59b JIT: revert cmpXX optimization 
It seems like this wasn't correct in 100% of cases.
 2014-11-03 17:50:20 -08:00
Fiora ce71c3cd4e JIT: fix valid_block marking 
This caused invalidations that only affected the last portion of a JIT block
to fail, breaking Wii64's block linking. It might affect a bunch of other
games too; I haven't tested.
 2014-11-03 16:23:44 -08:00
Fiora fc63c7ecae JIT: genericize immediate address handling, support in float stores too 2014-11-03 01:31:39 -08:00
Fiora e729fc4a28 JIT: fix dumb mistake in crclr optimization patch 2014-11-02 21:03:11 -08:00
Fiora 7deaf00c44 JIT: more mftb fixes 
A very subtle difference in how I calculated the timebase value seems
to have broken Karaoke Revolution; this seems to fix it. Also be a bit more
paranoid in conditions for mftb merging.
 2014-11-01 03:15:25 -07:00
Fiora fb0960f0ee JIT: flush unused registers during branch merges 
Also correct some flags in interpreter tables.
 2014-10-29 00:32:59 -07:00
Fiora 1ec1a9c33a JIT: optimize crclr special case of crxor 2014-10-29 00:30:27 -07:00
Fiora 97fba41860 JIT: merge fcmpx and cror 
Almost all uses of boolean condition-register ops in real code seem to be
the combination fcmpx + cror (e.g. for <= or >=). This merges the two.
 2014-10-29 00:30:27 -07:00
Fiora a666bb6bf6 JIT: optimize mulhwu 2014-10-29 00:30:26 -07:00
Fiora 5b5e462200 JIT: reorder blr comparisons 
This should allow macro-op fusion in blr instructions.
 2014-10-29 00:30:26 -07:00
Fiora 7388c62439 JIT: use BLR optimization to avoid anding LR with 0xFFFFFFFC 
Should save roughly one instruction per blr.
 2014-10-29 00:30:26 -07:00
Fiora cec2cb9d38 JIT: micro-optimize cmpXX a bit more for lower latency/code size 2014-10-29 00:30:25 -07:00
Fiora f4fa8d0b83 MMU: allow page-table loads/stores if MMU is off 
Fixes regressions in some games that apparently required this to work, but
don't really require full MMU emulation (e.g. with exceptions and all).
 2014-10-21 05:55:56 -07:00
Fiora d7ff482618 Fix FPRF flag setting 
Looks like I didn't quite change every place it needed to be renamed.
 2014-10-21 04:56:35 -07:00
Fiora d2e004fa9e Use CRC to output 64 bits instead of 32 
A bit hacky, but should dramatically reduce the odds of hash collision.
 2014-10-18 00:24:35 -07:00
Fiora c74b4df13e Add FPRF interface option, change from EnableFPRF to just FPRF 2014-10-17 19:06:18 -07:00
Fiora 719326df65 Make EnableBATs an option instead of disabling it entirely 2014-10-17 19:05:01 -07:00
Fiora 99169eb620 JIT: fix profiler on non-Windows OSs 
Still doesn't support timing code (since that's Windows-only), but run counts
will at least work without crashing.
 2014-10-17 16:48:09 -07:00
Fiora 15a4bccb73 Hash: unroll CRC loop, since CRC32 typically has nontrivial latency 
Seems to be about 20-30% faster texture cache hashing on my machine.
 2014-10-17 15:39:08 -07:00
Fiora 6ac2fcca61 MMU: disable BAT resolution 
No known games, not even Wii MMU games like Cars 2 and Toy Story 3, use custom
BATs. This makes BAT resolution a waste of time. BAT handling could be
optimized significantly, but as long as nothing uses it, it's easier to just
disable it.

Should significantly improve performance in MMU-heavy games.
 2014-10-13 22:04:03 -07:00
Fiora 7ba9a8537b JIT: add basic register allocation heuristics 
Should be at least a bit better than the previous LRU approach. Currently
has two basic components: whether a register is dirty (dirty registers need
to be stored, so clobbering them hurts more) and how many other registers will
be used between now and the next time a register gets used.

Also don't pre-load values that don't need to be in registers.
 2014-10-09 20:09:14 -07:00
Fiora 9d45f51459 JIT: fix accidental disabling of block linking by default 
Oops.
 2014-10-09 12:00:40 -07:00
Fiora 8bf2cf0641 Debug: fix disable block linking option 
Previously it did the opposite of what it was supposed to; when checked, it'd
turn block linking on, and when unchecked, it'd turn it off.

Also update JITIL's block linking disabling in debug mode to match the behavior
of the regular JIT.
 2014-10-08 19:03:25 -07:00
Fiora 75a1310ba9 CPU: improve instruction table flags for RC bits 2014-10-08 11:44:37 -07:00
Fiora 9734f0c834 JIT64: use FMA instructions 2014-10-07 21:41:01 -07:00
Fiora 4289221584 X64Emitter: add unit test for FMA 2014-10-07 18:21:07 -07:00
Fiora 019657cd93 X64Emitter: add FMA3 support 2014-10-07 18:21:07 -07:00
Fiora 5919d0962f JIT: re-add profiling support on x86_64 
Still gives rather inaccurate results with conditional continue and/or
branch merging on, so those should probably be turned off when using it.
 2014-10-06 20:26:58 -07:00
Fiora 9b29fe8aed WIP: don't let the backpatcher hit the same location twice 
If a location is hit by the backpatcher, don't fastmem it when recompiling the
block unless the block has actually been invalidated.
 2014-10-04 21:28:21 -07:00
Fiora 17c56b58ab JIT: set clear_cache_asap to false when clearing the cache 
Would probably result in continual cache-clearing if the stack overflow code
in the BLR optimizations triggers.
 2014-10-03 20:08:27 -07:00
Fiora bf014636c8 JIT: add more AVX support, reduce redundant XMM moves 
10-20% reduction in typical compiled block size for float-heavy JIT blocks.
 2014-10-03 16:17:08 -07:00
Fiora 8fe730194b JIT: load registers if they're going to be used later in the block 2014-10-03 11:58:04 -07:00
Fiora 6bff99fa75 JitAsmCommon: remove a few redundant moves 2014-10-03 10:05:42 -07:00
Fiora 7a2dd3a3c6 x64Emitter: refactor, add some new AVX instructions 2014-10-03 10:05:10 -07:00
Fiora 1bce0a847b Fix BAT register initial values in bootcode 
Probably won't affect any real things for now, since these BATs are already
hardcoded into the memory handling functions.
 2014-10-01 12:54:06 -07:00
Fiora 85547d94be JIT: properly remove FIFO write addresses when code is invalidated 
Fixes a bug caused by interaction with carry optimizations; might fix other
issues too.
 2014-09-30 01:00:23 -07:00
Fiora 22f087275c MMU: support loads/stores that cross page boundaries 
Fixes some strange issues with Rogue Squadron 3 in JIT mode.
 2014-09-29 21:19:21 -07:00
Fiora c102fed36a GekkoDisassembler: show W and I in psq_l/psq_st disassembly 2014-09-28 17:01:35 -07:00
Fiora 3878187721 Interpreter: remove debug printf in psq_l 2014-09-27 20:44:45 -07:00
Fiora fbbe9605a9 Debug: fix display of instructions in virtual memory in MMU games 2014-09-27 01:07:37 -07:00
Fiora ac1fc9ad03 JIT+Emitter: support locking flags 
This helps us avoid accidentally clobbering flags between two instructions
when the flags are expected to be maintained. Dolphin will of course crash
immediately, but at least it will crash loudly and alert us of the mistake,
instead of forcing hours of bisecting to find the subtle way in which the JIT
has managed to sneak a flag-modifying instruction where there shouldn't be one.
 2014-09-26 20:47:06 -07:00
Fiora 39d4306a2e JIT: fix carry merging across breakpoints 
More precisely, don't do it.
 2014-09-26 13:21:01 -07:00
Fiora ba39c35f24 JIT: fix branch merging, take 2 
NOT doesn't set flags.
 2014-09-25 22:33:40 -07:00
Fiora f9ab25152c JIT: fix bugs with ComputeRC in branch merging patch 
We really, really need to be sure the input to ComputeRC is a register.
 2014-09-25 21:45:25 -07:00
Fiora 23fbcecf13 JIT: enable block linking and idle skipping in debug mode 
They can still be turned off, just don't force them off.
Also remove some dated comments.
 2014-09-25 07:12:10 -07:00
Fiora bfab5f1e91 JIT: generic branch merging 
Why merge just cmps and rlwinm when we can merge ALL the branches?
 2014-09-24 12:34:18 -07:00
Fiora 5fce109ce1 Reorganize carry to store flags separately instead of part of XER 
Also correct behavior with regards to which bits in XER are treated as zero
based on a hwtest (probably doesn't affect any real games, but might as well
be correct).
 2014-09-24 12:27:47 -07:00
Fiora 88f2fbe1a4 JIT: fix merged bclr with comex's BLR optimizations 2014-09-22 18:22:31 -07:00
Fiora f103234e2b JIT: flush a register if it won't be used for the rest of the block 
This should dramatically reduce code size in the case of blocks with
lots of branches, and certainly doesn't hurt elsewhere either.

This can probably be improved a good bit through smarter tracking of register
usage, e.g. discarding registers that are going to be overwritten, but this
is a good start and should help reduce code size and register pressure.
Unlike that sort of change, this is a "safe" patch; it only flushes registers,
which can't affect correctness, unlike actually discarding data.

As part of this, refactor PPCAnalyst to support distinguishing between
float and integer registers (to properly handle instructions that access
both, like floating-point loads and stores).

Also update every instruction in the interpreter flags table I could find
that didn't have all the correct flags.
 2014-09-22 16:00:25 -07:00
Fiora de86d2003a JIT: merge lbz + extsb 
PPC has no 8-bit sign-extended load, so this instruction pair is very common.
x86 can do it in one op (movsx), so merge them when possible.
 2014-09-22 15:41:54 -07:00
Fiora 505b1bd562 JIT: a small optimization for subfex and friends 2014-09-21 12:16:26 -07:00
Fiora 9c4407fb80 Disassembler: fix disassembly of some twi instructions 2014-09-21 08:17:41 -07:00
Fiora 6043c790b6 JIT: fix indexed paired singles 
I didn't realize the I and W fields were in a different place for these
variants.

This should fix Paper Mario and probably lots of other things I accidentally
broke.
 2014-09-20 00:20:49 -07:00
Fiora 0f53bba45a JIT: change eieio and tlbsync to DoNothing 
The interpreter functions for these are no-ops anyways.
Also add some missing DoNothings to the ARM64 JIT.
 2014-09-19 13:14:49 -07:00
Fiora c130a496f2 JIT: fix fsel/ps_sel implementations for NaN input 
fselx was the main problem, but ps_sel was wrong too (even if there were no
known reported bugs with it).

This fixes Beyond Good and Evil (at the least).
 2014-09-19 01:58:13 -07:00
Fiora d96016ed21 JIT: support byte-reversed stores/loads 
4 more instructions down.

Store ones should be pretty well-tested; load ones seem to almost never be
used. I found them in Turok Evolution, so I was able to check code generation,
but the relevant code didn't seem to be called.
 2014-09-18 20:38:44 -07:00
Fiora af8772700a JIT: add ps_res and ps_rsqrte using scalar implementations 2014-09-18 18:36:15 -07:00
Fiora 1b425dedd1 JIT: add ps_cmp0/ps_cmp1 implementations using current fcmp code 2014-09-18 17:57:28 -07:00
Fiora 3c49200b22 X64Emitter: add MOVHLPS/MOVLHPS 2014-09-18 17:57:27 -07:00
Fiora 20c3a0f2d8 Debugger: scroll by multiples of 4 bytes 
Avoids that weird effect where scrolling offsets code from 4-byte boundaries,
showing nonsense 75% of the time.
 2014-09-18 03:54:57 -07:00
Fiora 8ce4676605 Debugger: make opcode search a bit better 
Search a wider range (not all games fit in the originally searched range).
Print a notice if the opcode isn't found, instead of silently failing.
 2014-09-18 03:47:46 -07:00
Fiora cd7853bd50 JIT: fix debug mode 2014-09-18 03:14:04 -07:00