Commit Graph
13 Commits
Author SHA1 Message Date
Sintendo 53a947749a x64Emitter: short MOV for 64bit immediates (2)
Prior to this commit, the emitter would unconditionally emit a 10-byte
instruction known as MOVABS when loading a 64-bit immediate to a
register.

0:  48 b8 ef be ad de 00    movabs rax,0xdeadbeef
7:  00 00 00

With this change, it will instead rely on the fact that on x64 writes to
32-bit registers are automatically zero extended to 64-bits, allowing
us to emit a 5 or 6-bytes instruction with the same effect for certain
immediates.

0:  b8 ef be ad de          mov    eax,0xdeadbeef
2018-09-16 19:52:03 +02:00
Sintendo 575f1b309a x64Emitter: short MOV for 64bit immediates (1)
Prior to this commit, the emitter would unconditionally emit a 10-byte
instruction known as MOVABS when loading a 64-bit immediate to a
register.

0:  48 b8 ef be ad de ff    movabs rax,0xffffffffdeadbeef
7:  ff ff ff

With this change, it will instead emit a 7-byte instruction when it is
possible to express the 64-bit immediate using a signed 32-bit value.

0:  48 c7 c0 ef be ad de    mov    rax,0xffffffffdeadbeef
2018-09-14 23:11:26 +02:00
Sintendo 78bc9690e2 Eliminate branch in ConvertDoubleToSingle 2018-06-13 23:02:50 +02:00
Sintendo f163bd1048 Fix various comment typos 2016-10-24 18:27:49 +02:00
Sintendo 00cc59e83a VideoInterface: Fix comment typo 2016-02-21 09:39:01 +01:00
Sintendo c4b56f06f9 Fix a few typos 2015-11-02 21:17:43 +01:00
Sintendo ce10525056 Eliminate branch in GenFres 2015-07-05 11:18:59 +02:00
Sintendo c19482c9a3 Add function to emit CMP, or TEST when possible
Also, a spelling mistake.
2015-03-22 17:22:27 +01:00
Sintendo b35c34186c More minor DSP JIT optimizations 2015-03-22 17:14:38 +01:00
Sintendo 46df8a5358 Correct clobber comments 2015-02-04 22:26:40 +01:00
Sintendo ca0790e9c9 Merge Update_SR_Register64_Carry functions 2015-02-04 22:26:40 +01:00
Sintendo 34afe08de9 Minor DSP JIT optimizations 2015-02-04 22:26:39 +01:00
Sintendo 29cca5c84f Change fres/frsqrte jumps 2014-09-24 21:58:01 +02:00