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Author SHA1 Message Date
MerryMage 1ab7657120 MovI2R: Do not exhaustively test 2021-01-31 13:17:31 +00:00
MerryMage fe9207bb56 UnitTests: Add MOVI2R test 2021-01-31 13:17:19 +00:00
MerryMage f65c1df094 Random: Add seeded PRNG 2021-01-31 13:16:45 +00:00
MerryMage a0b8956f22 JitArm64_Integer: Add optimizations for rlwimix 
* Check for case when source field is at LSB
* Use BFXIL if possible
* Avoid ROR where possible
 2021-01-31 12:05:43 +00:00
MerryMage 8aa2013a2d Arm64Emitter: Add additional assertions to BFI/UBFIZ 2021-01-31 12:04:57 +00:00
MerryMage 75d92ad628 Arm64Emitter: Prefer BFM/UBFM to EncodeBitfieldMOVInst 2021-01-31 12:04:57 +00:00
MerryMage be6aec9932 Arm64Emitter: Add BFXIL 2021-01-31 12:04:57 +00:00
MerryMage 6106d6481f BitUtils: __builtin_clz is undefined when value == 0 2021-01-03 17:35:15 +00:00
MerryMage 8ae0bf93e7 JitArm64: Do not use offsetof on non-standard-layout types 
Applying PR #8687 to Arm64 JIT.
 2021-01-03 15:26:01 +00:00
MerryMage 14c03388b3 Externals: Link against required libraries 
* curl requires zlib
* hidapi when not using libudev requires libusb
 2021-01-03 14:26:38 +00:00
merryandSintendo 71a996e33b Jit_Integer: srawx: Handle a != b case with SARX 
Suggested by @Sintendo

Co-authored-by: Sintendo <[email protected]>
 2021-01-01 10:32:01 +00:00
MerryMage d3ca5d812b Jit_Integer: Use SHLX, SHRX, SARX 2020-12-29 23:51:54 +00:00
MerryMage cdcca72b61 Jit_Integer: Optimize common rlwimix cases 2020-12-28 12:57:53 +00:00
MerryMage 4a102186c7 Jit_Integer: rlwimix: Handle all gpr.IsImm(a) cases 2020-12-28 12:55:39 +00:00
MerryMage c20bb81071 Jit_Integer: rlwimix: Flatten logic 2020-12-28 12:53:24 +00:00
MerryMage 0ef1fcdeb9 Jit_Integer: rlwinix: Handle immediate mask == 0xFFFFFFFF case 2020-12-28 12:49:48 +00:00
MerryMage 19aa10df75 Jit_Integer: rlwimix: Fix bug in mask == 0xFFFFFFFF case 2020-12-28 12:48:03 +00:00
MerryMage 4e0a688076 Jit_Integer: rlwnmx: Use RotateLeft 2020-12-28 12:47:03 +00:00
MerryMage e415580f54 Jit_Integer: Use Common::CountLeadingZeros in cntlzwx 2020-12-28 01:08:50 +00:00
MerryMage 7e9824611e Interpreter_Integer: Use Common::CountLeadingZeros in cntlzwx 2020-12-28 01:08:50 +00:00
MerryMage d695fcb126 BitUtils: Add CountLeadingZeros 2020-12-27 22:56:43 +00:00
MerryMage 73b6166f18 Jit_Integer: rlwinmx: Use BEXTR where possible 2020-12-27 15:08:45 +00:00
MerryMage 11643ee2f0 Jit_Integer: rlwinmx: Generalize byte/word extract plus shift case 2020-12-27 14:43:51 +00:00
MerryMage bea6a86893 Jit_Integer: Add trivial AndWithMask cases 
Add cases to handle all one and all zero masks.
 2020-12-27 00:18:06 +00:00
MerryMage 946e1b9054 Jit_Integer: Missed AndWithMask in rlwimix 2020-12-26 23:33:33 +00:00
MerryMage e1024fc6ba Jit_Integer: Use RORX where possible 2020-12-26 23:00:04 +00:00
MerryMage d109451ad5 Analytics: Add rarer OSes to analytics 2020-12-20 22:32:07 +00:00
MerryMage 29fceeb37f MemoryUtil: Use HW_PHYSMEM64 sysctl in MemPhysical 
HW_PHYSMEM is deprecated on OpenBSD and only supplies a 32-bit value on NetBSD
 2020-12-20 22:25:36 +00:00
MerryMage a10447eae2 JitArm64_Paired: Fix ps_msub when d == b 2020-07-01 20:11:54 +01:00
MerryMage f6afce781f Jit64AsmCommon: Use PEXT in GenConvertDoubleToSingle 2019-05-25 23:07:50 +01:00
MerryMage 12314577c1 Jit64AsmCommon: Make ConvertDoubleToSingle use RSCRATCH as output 2019-05-25 23:07:50 +01:00
MerryMage ec8d57d882 UnitTests/Jit64Common: Test GenConvertDoubleToSingle 2019-05-25 23:07:50 +01:00
MerryMage e06111e86f EmuCodeBlock: Prefer MOVAPS to MOVSD in ConvertDoubleToSingle 
* The high half of the register is immediately masked so the value in it is irrelevant.
* MOVSD produces an unnecessary dependency on the high half of regOp.
* MOVAPS is implemented as a register rename on modern microarchitectures.
 2019-04-27 12:57:03 +01:00
MerryMage 1baa8ee970 x64Emitter: Prefer MOVAPS to MOVSD 
* The high half of regOp is immediately overwritten so the value in it is irrelevant.
* MOVSD produces an unnecessary dependency on the high half of regOp.
* MOVAPS is implemented as a register rename on modern microarchitectures.
 2019-04-27 12:56:05 +01:00
MerryMage 2d4dd8cdc1 x64Emitter: Prefer MOVAPS to MOVAPD 
There is no reason to use MOVAPD over MOVAPS, for two reasons:
* There has never been a microarchitecture with separate single and double domains.
* MOVAPD is one byte longer than MOVAPS
 2019-04-27 12:54:43 +01:00
MerryMage e4d83a56a5 EmuCodeBlock: Correct zero handling in SetFPRF for SSE4.1 2019-04-12 20:03:42 +01:00
MerryMage 77e9aa48bc Jit64: Remove Jitx86Base class 2018-12-28 09:15:26 +00:00
MerryMage 26bc38d25d Jit64: Fix instruction breakpoints 
Broken by 5236dc3.
 2018-12-27 20:11:26 +00:00
MerryMage b7b552f20a x64EmitterTest: Add some missing tests 2018-12-26 15:22:45 +00:00
MerryMage da7608ff9f x64Emitter: Add some single-precision instructions 2018-12-26 00:23:42 +00:00
MerryMage 0deed2a5af EmuCodeBlock: Fix bug in SetFPRF: Should only consider lower double 2018-12-24 19:02:43 +00:00
MerryMage 5236dc31a6 Jit64: Check downcount at block exit, not block entry 2018-12-23 18:03:29 +00:00
MerryMage 174d2b0230 crXXX: Avoid loading twice when CRBA == CRBB 2018-12-21 11:33:18 +00:00
MerryMage 07c146e7e2 crXXX: Remove unnecessary CRBA == CRBD constraint for crclr and crset 2018-12-21 11:20:06 +00:00
MerryMage df08a77812 Jit_LoadStore: Ra needs to be ReadWrite when writeback is required 
This was an erronous change in 534db3b, Ra was previously loaded but was changed to not being loaded.
Why is loading necessary? Loading is necessary because when a memory exception occurs, the current
register values are flushed. This occurs before a new value is loaded into Ra, so the previous value
is required in Ra.
 2018-11-10 10:57:15 +00:00
MerryMage 342067abfa JitRegCache: Remove old interface 2018-10-28 17:57:46 +00:00
MerryMage 08c41090b2 JitRegCache: Add RegistersInUse 2018-10-28 17:57:46 +00:00
MerryMage 096392f295 JitRegCache: Add PreloadRegisters function 2018-10-28 17:57:46 +00:00
MerryMage 9f683f9bb1 BitSet: Add << operator 2018-10-28 17:57:46 +00:00
MerryMage e699b6b283 Jit: Remove OpArg variant of ComputeRC 2018-10-28 17:57:46 +00:00
MerryMage 7d7316c90f Jit_SystemRegisters: mffsx 2018-10-28 17:57:46 +00:00
MerryMage 62484141f2 Jit_SystemRegisters: mtfsfx 2018-10-28 17:57:46 +00:00
MerryMage 192f8ba6f1 Jit_Paired: ps_res 2018-10-28 17:57:46 +00:00
MerryMage 66d9349643 Jit_Paired: ps_rsqrte 2018-10-28 17:57:45 +00:00
MerryMage 3fc3a55a9a Jit_Paired: mergeXX 2018-10-28 17:57:45 +00:00
MerryMage cf5823c146 Jit_Paired: ps_muls 2018-10-28 17:57:45 +00:00
MerryMage 1550729688 Jit_Paired: ps_sum 2018-10-28 17:57:45 +00:00
MerryMage be8fec6244 Jit_Paired: ps_mr 2018-10-28 17:57:45 +00:00
MerryMage 96b86a9bc4 Jit_FloatingPoint: HandleNaNs 2018-10-28 17:57:45 +00:00
MerryMage 0a96da578e Jit_FloatingPoint: fresx 2018-10-28 17:57:45 +00:00
MerryMage e812a62879 Jit_FloatingPoint: frsqrtex 2018-10-28 17:57:45 +00:00
MerryMage 68bbd56c01 Jit_FloatingPoint: frspx 2018-10-28 17:57:45 +00:00
MerryMage cc77e2f3ef Jit_FloatingPoint: fctiwx 2018-10-28 17:57:45 +00:00
MerryMage 457327cbc4 Jit_FloatingPoint: FloatCompare 2018-10-28 17:57:45 +00:00
MerryMage 55c21a15a2 Jit_FloatingPoint: fmrx 2018-10-28 17:57:45 +00:00
MerryMage fecbf091e5 Jit_FloatingPoint: fselx 2018-10-28 17:57:45 +00:00
MerryMage d62ca40496 Jit_FloatingPoint: fsign 2018-10-28 17:57:45 +00:00
MerryMage 537eeb7ebf Jit_FloatingPoint: fmaddXX 2018-10-28 17:57:45 +00:00
MerryMage a26c9c4b74 Jit_FloatingPoint: fp_arith 2018-10-28 17:57:45 +00:00
MerryMage 2337e089bf Jit_SystemRegisters: mtspr 2018-10-28 17:57:45 +00:00
MerryMage d87436c57d Jit_LoadStorePaired: psq_lXX 2018-10-28 17:57:45 +00:00
MerryMage 0b29b5cb83 Jit_LoadStorePaired: psq_stXX 2018-10-28 17:57:45 +00:00
MerryMage 459f977483 Jit_LoadStoreFloating: stfiwx 2018-10-28 17:57:45 +00:00
MerryMage dcfe955087 Jit_LoadStoreFloating: stfXXX 2018-10-28 17:57:45 +00:00
MerryMage f564da7233 Jit_LoadStoreFloating: lfXXX 2018-10-28 17:57:45 +00:00
MerryMage 36790ad3ad Jit_SystemRegisters: mtcrf 2018-10-28 17:57:45 +00:00
MerryMage d8b2bf785a Jit_SystemRegisters: mfcr 2018-10-28 17:57:45 +00:00
MerryMage 6ff8f9e991 Jit_SystemRegisters: mfmsr 2018-10-28 17:57:45 +00:00
MerryMage 5fa6df8c1e Jit_SystemRegisters: mtmsr 2018-10-28 17:57:45 +00:00
MerryMage 1d867493d9 Jit_SystemRegisters: mfspr 2018-10-28 17:57:45 +00:00
MerryMage 9438ea0ef5 Jit_LoadStore: stmw 2018-10-28 17:57:45 +00:00
MerryMage 98cf0b3286 Jit_LoadStore: lmw 2018-10-28 17:57:45 +00:00
MerryMage c6b9712ac4 Jit_LoadStore: stXx 2018-10-28 17:57:44 +00:00
MerryMage 90cef22d57 Jit_LoadStore: stX 2018-10-28 17:57:44 +00:00
MerryMage 4a2efc8f5e Jit_LoadStore: dcbz 2018-10-28 17:57:44 +00:00
MerryMage 0e501e5c36 Jit_LoadStore: dcbx 2018-10-28 17:57:44 +00:00
MerryMage 534db3b2ed Jit_LoadStore: lXXx 2018-10-28 17:57:44 +00:00
MerryMage 00d65f7a69 Jit: memcheck 2018-10-28 17:57:44 +00:00
MerryMage c896d41c37 DoJit 2018-10-28 17:57:44 +00:00
MerryMage 4443b36326 Jit_Branch: bclrx 2018-10-28 17:57:44 +00:00
MerryMage 0cd85bbce7 Jit_Branch: bcctrx 2018-10-28 17:57:44 +00:00
MerryMage 453417ad8c Jit_Branch: bcx 2018-10-28 17:57:44 +00:00
MerryMage 256e234949 Jit_Integer: DoMergedBranchCondition 2018-10-28 17:57:44 +00:00
MerryMage 0d3393b306 Jit_Integer: rlwimix 2018-10-28 17:57:44 +00:00
MerryMage b866b5bdd9 Jit_Integer: reg_imm 2018-10-28 17:57:44 +00:00
MerryMage ace2ed27ac Jit_Integer: DoMergedBranchImmediate 2018-10-28 17:57:44 +00:00
MerryMage 88e5d0d8b1 Jit_Integer: cmpXX 2018-10-28 17:57:44 +00:00
MerryMage b256286690 Jit_Integer: boolX 2018-10-28 17:57:44 +00:00
MerryMage b7a4296bec Jit_Integer: extsXx 2018-10-28 17:57:44 +00:00
MerryMage c380764ed0 Jit_Integer: twX 2018-10-28 17:57:44 +00:00