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Author SHA1 Message Date
Fiora c102fed36a GekkoDisassembler: show W and I in psq_l/psq_st disassembly 2014-09-28 17:01:35 -07:00
Fiora 3878187721 Interpreter: remove debug printf in psq_l 2014-09-27 20:44:45 -07:00
Fiora fbbe9605a9 Debug: fix display of instructions in virtual memory in MMU games 2014-09-27 01:07:37 -07:00
Fiora 39d4306a2e JIT: fix carry merging across breakpoints 
More precisely, don't do it.
 2014-09-26 13:21:01 -07:00
Fiora ba39c35f24 JIT: fix branch merging, take 2 
NOT doesn't set flags.
 2014-09-25 22:33:40 -07:00
Fiora f9ab25152c JIT: fix bugs with ComputeRC in branch merging patch 
We really, really need to be sure the input to ComputeRC is a register.
 2014-09-25 21:45:25 -07:00
Fiora 23fbcecf13 JIT: enable block linking and idle skipping in debug mode 
They can still be turned off, just don't force them off.
Also remove some dated comments.
 2014-09-25 07:12:10 -07:00
Fiora bfab5f1e91 JIT: generic branch merging 
Why merge just cmps and rlwinm when we can merge ALL the branches?
 2014-09-24 12:34:18 -07:00
Fiora 5fce109ce1 Reorganize carry to store flags separately instead of part of XER 
Also correct behavior with regards to which bits in XER are treated as zero
based on a hwtest (probably doesn't affect any real games, but might as well
be correct).
 2014-09-24 12:27:47 -07:00
Fiora 88f2fbe1a4 JIT: fix merged bclr with comex's BLR optimizations 2014-09-22 18:22:31 -07:00
Fiora f103234e2b JIT: flush a register if it won't be used for the rest of the block 
This should dramatically reduce code size in the case of blocks with
lots of branches, and certainly doesn't hurt elsewhere either.

This can probably be improved a good bit through smarter tracking of register
usage, e.g. discarding registers that are going to be overwritten, but this
is a good start and should help reduce code size and register pressure.
Unlike that sort of change, this is a "safe" patch; it only flushes registers,
which can't affect correctness, unlike actually discarding data.

As part of this, refactor PPCAnalyst to support distinguishing between
float and integer registers (to properly handle instructions that access
both, like floating-point loads and stores).

Also update every instruction in the interpreter flags table I could find
that didn't have all the correct flags.
 2014-09-22 16:00:25 -07:00
Fiora de86d2003a JIT: merge lbz + extsb 
PPC has no 8-bit sign-extended load, so this instruction pair is very common.
x86 can do it in one op (movsx), so merge them when possible.
 2014-09-22 15:41:54 -07:00
Fiora 505b1bd562 JIT: a small optimization for subfex and friends 2014-09-21 12:16:26 -07:00
Fiora 9c4407fb80 Disassembler: fix disassembly of some twi instructions 2014-09-21 08:17:41 -07:00
Fiora 6043c790b6 JIT: fix indexed paired singles 
I didn't realize the I and W fields were in a different place for these
variants.

This should fix Paper Mario and probably lots of other things I accidentally
broke.
 2014-09-20 00:20:49 -07:00
Fiora 0f53bba45a JIT: change eieio and tlbsync to DoNothing 
The interpreter functions for these are no-ops anyways.
Also add some missing DoNothings to the ARM64 JIT.
 2014-09-19 13:14:49 -07:00
Fiora c130a496f2 JIT: fix fsel/ps_sel implementations for NaN input 
fselx was the main problem, but ps_sel was wrong too (even if there were no
known reported bugs with it).

This fixes Beyond Good and Evil (at the least).
 2014-09-19 01:58:13 -07:00
Fiora d96016ed21 JIT: support byte-reversed stores/loads 
4 more instructions down.

Store ones should be pretty well-tested; load ones seem to almost never be
used. I found them in Turok Evolution, so I was able to check code generation,
but the relevant code didn't seem to be called.
 2014-09-18 20:38:44 -07:00
Fiora af8772700a JIT: add ps_res and ps_rsqrte using scalar implementations 2014-09-18 18:36:15 -07:00
Fiora 1b425dedd1 JIT: add ps_cmp0/ps_cmp1 implementations using current fcmp code 2014-09-18 17:57:28 -07:00
Fiora 3c49200b22 X64Emitter: add MOVHLPS/MOVLHPS 2014-09-18 17:57:27 -07:00
Fiora 20c3a0f2d8 Debugger: scroll by multiples of 4 bytes 
Avoids that weird effect where scrolling offsets code from 4-byte boundaries,
showing nonsense 75% of the time.
 2014-09-18 03:54:57 -07:00
Fiora 8ce4676605 Debugger: make opcode search a bit better 
Search a wider range (not all games fit in the originally searched range).
Print a notice if the opcode isn't found, instead of silently failing.
 2014-09-18 03:47:46 -07:00
Fiora cd7853bd50 JIT: fix debug mode 2014-09-18 03:14:04 -07:00
Fiora 9ab816e6e9 JIT: fix regression in ps_sel 
My code didn't maintain correct semantics with floating-point NaNs (a < b is
not the same as "not a >= b" in float), which seems to have broken FIFA 12.
 2014-09-17 21:43:44 -07:00
Fiora 29fc151cc7 JIT: implement remaining psq_l/st instruction variants 
These are used in at least a few popular games, including Super Smash Bros.
Brawl.
 2014-09-17 17:10:27 -07:00
Fiora cfd65c2762 JIT: rename a few constants to be more accurate 
Remove the '2'; it's not longer applicable.
 2014-09-17 16:59:35 -07:00
Fiora 2a0b06f08c JIT: simpler fallback conditions for load/store float 
I wasn't really thinking when I wrote these; d/s are for float registers, not
gprs.
 2014-09-17 10:27:33 -07:00
Fiora 76c8bb40e8 JIT: update some rather outdated comments 2014-09-16 23:42:22 -07:00
Fiora 2ae6f13d22 JIT: use cvtsi2ss in paired singles 
One less instruction for a few of the loads.
 2014-09-16 22:50:33 -07:00
Fiora d3dee1d7ed GekkoDisassembler: fix some float opcodes 2014-09-16 02:06:40 -07:00
Fiora 7368c2ee9e GekkoDisassembler: fix/improve disassembly for a few instructions 2014-09-15 18:48:54 -07:00
Fiora 764ce4b513 JIT: add fselx implementation 
Based on a patch by Tilka.
 2014-09-15 08:33:41 -07:00
Fiora 7ab820c6f8 JIT: Various JitAsmCommon optimizations 
Use some SSE4 instructions in on CPUs that support them.
Use float instructions instead of int where appropriate (it's a cycle faster
on CPUs with arithmetic unit forwarding penalties).
 2014-09-15 08:33:40 -07:00
Fiora 7b0f559ae1 JIT: various float optimizations 2014-09-15 08:33:40 -07:00
Fiora 34287b8042 JIT: some paired singles optimizations 2014-09-15 08:33:39 -07:00
Fiora d02b7c7755 JIT: support immediate stores 2014-09-15 07:25:32 -07:00
Fiora 02dce5dbbf x64Emitter: fix silent failure if WriteNormalOp is passed two memory operands 
Should now fail loudly and clearly instead.
 2014-09-15 07:08:08 -07:00
Fiora a248e49c97 Revert "Two small JIT optimizations" 2014-09-15 07:01:51 -07:00
Fiora 3845c27155 JIT: save an instruction in psq_l 2014-09-14 15:12:57 -07:00
Fiora af471d0a84 JIT: optimize andi(s)_rc 
We usually don't need to do a sign-extend for the resulting flags.
 2014-09-14 15:12:14 -07:00
Fiora 9b8cfcdc29 Interpreter: fix carry calculation in srawx 
I don't know anything this affected, but it didn't match the manual (or JIT).
 2014-09-14 15:08:57 -07:00
Fiora 40b18f09b2 JIT: use LZCNT in cntlzw 2014-09-14 05:36:23 -07:00
Fiora 997c5c2d0e x64Emitter: add LZCNT/TZCNT support and detection 
Also add a unit test.
 2014-09-14 05:31:22 -07:00
Fiora 653140fcfa MMU: properly check MEM1 range on Gamecube games 
Fixes at the very least Rogue Squadron II crashes.
 2014-09-14 00:16:37 -07:00
Fiora 9d2b2cae4a JIT: fix JIT with conditional continue off, again 2014-09-14 00:12:27 -07:00
Fiora 1bd8d1ee98 Add immediate tests for WriteNormalOp 
also fix a bug in Bochs that was preventing adc from passing.
 2014-09-13 16:39:34 -07:00
Fiora 32a67ef264 JIT: fix memcheck on float load/store, plus some corner cases 2014-09-13 13:53:19 -07:00
Fiora b3c1cec197 JIT: fix memcheck with stXx 2014-09-13 13:53:18 -07:00
Fiora 9a19314969 JIT: make memcheck macro support an inverted mode 2014-09-13 13:53:13 -07:00
Fiora 54e26f64c6 JIT: use far code emitter in more places 2014-09-13 13:51:12 -07:00
Fiora 08ac10d00a PPCAnalyst/JIT: add ability to easily toggle branch and carry merging 2014-09-13 13:48:24 -07:00
Fiora 54129a8ca5 PPCAnalyst: refactor, add carry op reordering and non-cmp reordering 
Tries as hard as possible to push carry-using operations (like addc and adde)
next to each other. Refactor the instruction reordering to be more flexible
and allow multiple passes.

353 -> 192 x86 instructions on a carry-heavy code block in Pokemon Puzzle.
12% faster overall in Pokemon Puzzle; probably less in typical games (Virtual
Console games seem to be carry-heavy for some reason; maybe a different
compiler?)
 2014-09-13 13:48:23 -07:00
Fiora 45d84605a9 JIT64: optimize carry calculations further 
Keep carry flags in the x86 flags register if used in the next instruction.
 2014-09-13 13:48:20 -07:00
Fiora bea2504a51 JIT64: optimize carry calculations 
Omit carry calculations that get overwritten later in the block before they're
used. Very common in the case of srawix and friends.
 2014-09-13 13:47:43 -07:00
Fiora c5381bae66 JIT: add "far code emitter" to reduce L1I cache pressure 2014-09-13 02:31:31 -07:00
Fiora 09a62505c5 JIT: support paired load/store with MMU on 
Also change the calling convention, to avoid RSCRATCH being clobbered by
memcheck'd loads.
 2014-09-13 02:18:11 -07:00
Fiora 2661bc151a JIT memcheck: don't flush register state unless an exception occurs 2014-09-12 20:55:00 -07:00
Fiora a6c9515b00 JIT: unify subfcx and addcx code 
Again, shorter and should make future optimizations easier.
 2014-09-12 00:04:42 -07:00
Fiora 5d80145dc0 JIT: unify subfe/submex/subfex/adde/addmex/addzex code 
Shorter, plus should make future optimizations easier.
 2014-09-12 00:04:42 -07:00
Fiora 18d83a310e X64Emitter: support shorter mov reg, imm opcodes 
Also refactor WriteNormalOp a little bit and add comments.
 2014-09-11 11:40:30 -07:00
Fiora 5726e0cdfb JIT: use XCHG in MOVTwo 
Roughly the same speed or slightly faster depending on CPU; mostly just cleaner
since we don't have to pass in a temp.
 2014-09-10 22:17:38 -07:00
Fiora b3a57ff396 JIT: remove op merging code that served no purpose 
Dolphin already tracks propagation of immediates, so this code didn't really do
anything useful.
 2014-09-09 18:09:23 -07:00
Fiora 0af1352020 JIT: fix running in debug mode 
Regression in 7fb6628.
 2014-09-08 21:11:41 -07:00
Fiora 8fc57d61ba JIT64: support merged branching for rlwinmx, too 
Not quite as common a branch instruction as cmpwi, but close.
 2014-09-08 20:16:41 -07:00
Fiora b56117de05 JIT64: optimize some special cases of srawix 
Shift by 31 and 1, both of which are pretty common, can be done in a few less
instructions. Tested with a hwtest.
 2014-09-08 20:15:49 -07:00
Fiora a95d8cbcb4 JIT64: optimize carry handling 
Carries are rather common and unpredictable, so do them branchlessly wherever
we can.
 2014-09-08 20:15:49 -07:00
Fiora a570c6b4a4 JIT64: tweak srwx/slwx BindToRegister arguments 
Register B gets immediately moved into the shift register, so even if a == b
it doesn't need to be loaded.
 2014-09-08 20:15:49 -07:00
Fiora 5b77617069 JIT64: use LEA for the "a = b + imm" case of addi 2014-09-08 20:15:48 -07:00
Fiora 9977da0550 JIT64: avoid using LEA for adds when not necessary 2014-09-08 20:15:48 -07:00
Fiora 298f85e152 JIT64: optimize sign-extend 
Remove some code duplication.

Also remove some comments that no longer apply since x86_32 was dropped.
 2014-09-08 20:15:47 -07:00
Fiora faf6bdfd96 JIT64: Optimize cmpXX 
Use TEST instead of CMP if we're comparing against 0 (rather common), and
optimize the case of immediate compares further.
 2014-09-08 20:15:47 -07:00
Fiora de662a79b7 JIT64: optimize rlwinmx/rlwinix and friends 
Take advantage of movzx as a replacement for anding with 0xff or 0xffff, and
abuse loads from the register cache to save ops.
 2014-09-08 20:15:46 -07:00
Fiora 858296e1c7 JIT64: optimize multiplication by immediate constants 
Factor out common code and handle a few more common cases.
 2014-09-08 20:15:46 -07:00
Fiora 94c20db369 Rename Log2 and add IsPow2 to MathUtils for future use 
Also remove unused pow2/pow2f functions.
 2014-09-08 20:15:45 -07:00
Fiora ce494a5e4f JIT: fix a corner case in crXXX 
It didn't behave correctly with an input of zero, resulting in some games
breaking (at the least, Fight Night 2). This should be fixed now.

Also clean it up, add a few comments, and fix some variants of the instruction
that are so rare that they probably never got tested.
 2014-09-08 04:16:50 -07:00
Fiora 3855396422 JIT: fix conditional-continue=off 2014-09-08 00:28:56 -07:00
Fiora 4ec8f83a1a JIT: fix branch merging with bclr 2014-09-05 13:58:06 -07:00
Fiora 801153301f Remove debug printf from earlier commit 2014-09-05 10:31:29 -07:00
Fiora 07e0c917c6 Revert "JIT64: optimize CA calculations" 2014-09-05 10:26:30 -07:00
Fiora 2f9e9bf1fc JIT: completely inline timer reading 
Should be a bit faster on games that heavily use the timer.
 2014-09-04 21:55:36 -07:00
Fiora a63b9f6713 JIT: remove srawix fallback 
As far as I can tell, this has literally been here since the start of the git
history; maybe it was stubbed out because the author wasn't sure it was right?

It matches the PPC/Broadway manuals perfectly, though.
 2014-09-03 23:39:52 -07:00
Fiora 068b5c26f4 JIT: fix regression in timer patch 2014-09-03 14:36:38 -07:00
Fiora 1b50f9df14 JIT: implement fres 
Mostly a straightforward translation of the interpreter code, with a few
tricksy optimizations and fallbacks for rare paths.
 2014-09-03 12:15:30 -07:00
Fiora c72a133206 JIT: implement frsqrte 
Mostly a straightforward translation of the interpreter code, with a few
tricksy optimizations and fallbacks for rare paths.
 2014-09-03 11:21:04 -07:00
Fiora 5088a2b4e2 x64Emitter: add BMI1/BMI2 support 
TZCNT and LZCNT use a completely different encoding scheme, so they should
probably go in a separate patch.

Also add some tests.
 2014-09-03 10:04:01 -07:00
Fiora 9e4419e786 x64Emitter: add support for shorter EAX forms of instructions 
Should save a few bytes of code size here and there.
 2014-09-02 21:52:41 -07:00
Fiora 6875d911f1 JIT: merge paired timebase reads where possible 
Combined with the previous patch, ~1% faster overall on F-Zero GX.
 2014-09-02 21:49:24 -07:00
Fiora 816d056657 JIT: implement timer support in mtspr 
Faster, of course, since we avoid the interpreter, but also means we can
get more a more accurate timer in long blocks by adding the offset from the
start of the block to the retrieved timer. I don't know if this will actually
fix any issues, but it's more correct and a nearly-free improvement.
 2014-09-02 21:47:45 -07:00
Fiora 6655c7775e JIT: Fix callee-save registers on WIN64 2014-09-02 10:56:14 -07:00
Fiora 3aa40dab00 JIT64: optimize carry calculations 
Omit carry calculations that get overwritten later in the block before they're
used. Very common in the case of srawix and friends.
 2014-09-01 20:41:48 -07:00
Fiora a40278b1c4 JIT64: support merged branching for rlwinmx, too 
Not quite as common a branch instruction as cmpwi, but close.
 2014-09-01 20:41:12 -07:00
Fiora 10d691a277 JIT64: optimize some special cases of srawix 
Shift by 31 and 1, both of which are pretty common, can be done in a few less
instructions. Tested with a hwtest.
 2014-09-01 20:41:12 -07:00
Fiora 805be80f12 JIT64: Optimize carry handling 
Carries are rather common and unpredictable, so do them branchlessly wherever
we can.
 2014-09-01 20:41:11 -07:00
Fiora ee24d4714a JIT64: tweak srwx/slwx BindToRegister arguments 
Register B gets immediately moved into the shift register, so even if a == b
it doesn't need to be loaded.
 2014-09-01 20:41:11 -07:00
Fiora ad51fc7c4b JIT64: use xor instead of mov for loading a zero regcache immediate 2014-09-01 20:41:10 -07:00
Fiora 27996a65cf JIT64: use LEA for the "a = b + imm" case of addi 2014-09-01 20:41:10 -07:00
Fiora cd0c52b537 JIT64: avoid using LEA for adds when not necessary 2014-09-01 20:41:10 -07:00
Fiora 355850f499 JIT64: optimize sign/zero-extend 
Also remove some comments that no longer apply since x86_32 was dropped.
 2014-09-01 20:41:09 -07:00
Fiora 61af91ff16 JIT64: Optimize cmpXX 
Use TEST instead of CMP if we're comparing against 0 (rather common), and
optimize the case of immediate compares further.
 2014-09-01 20:41:09 -07:00