The computed value is only used when the register is equal to zero, so
we can fully precompute it and materialize the constant instead. In
other words, we change from
```
return reg == 0 ? (reg | 1ULL << 63) : reg;
```
to
```
return reg == 0 ? 1ULL << 63 : reg;
```
The number of instructions remains the same, but we eliminate an
unnecessary dependency on the register value.
Before:
0xb241037a orr x26, x27, #0x8000000000000000
0xeb1f037f cmp x27, xzr
0x9a9a137b csel x27, x27, x26, ne
After:
0xd2f0001a mov x26, #-0x8000000000000000 ; =-9223372036854775808
0xeb1f037f cmp x27, xzr
0x9a9a137b csel x27, x27, x26, ne
When the input register and carry flags are known, we can always
precompute the result.
We still materialize the immediate when the condition register
needs to be updated, but this seems to be a general problem. I might
look into that one day, but for now this'll do.
- ConstantFalse
Before:
0x52800119 mov w25, #0x8 ; =8
0x2a1903fa mov w26, w25
After:
N/A
- ConstantTrue
Before:
0x52800119 mov w25, #0x8 ; =8
0x1100073a add w26, w25, #0x1
After:
N/A
Same optimization we did for subfex. Skip loading the carry flag into a
temporary register first when we're dealing with zero.
Before:
0x394bd3b8 ldrb w24, [x29, #0x2f4]
0x2a1803f9 mov w25, w24
After:
0x394bd3b9 ldrb w25, [x29, #0x2f4]
When both the input register and the carry flag are constants, the
result can be precomputed.
Before:
0x52800016 mov w22, #0x0 ; =0
0x2a3603f6 mvn w22, w22
After:
The result is either -1 or 0 depending on the state of the carry flag.
This can be done with a csetm instruction.
Before:
0x1280001a mov w26, #-0x1 ; =-1
0x1a1f035a adc w26, w26, wzr
After:
0x5a9f23fa csetm w26, lo
When the immediate is zero, we can load the carry flag from memory
directly to the destination register.
Before:
0x394bd3b8 ldrb w24, [x29, #0x2f4]
0x2a1803f9 mov w25, w24
After:
0x394bd3b9 ldrb w25, [x29, #0x2f4]
Prefer BLENDVPD over VBLENDVPD if the latter doesn't save any
instructions.
VBLENDVPD allows separate source and destination registers, which can
eliminate a MOVAPD/MOVSD. However, on Intel since Skylake, VBLENDVPD
takes additional uops to execute compared to BLENDVPD (according to
https://uops.info). On AMD and older Intel microarchitectures there is no
difference.
The value being stored must be loaded into a register. In the case of an
immediate value, this means it must be materialized. The value is
eventually byteswapped before performing the store.
This can be simplified for the value 0 for two reasons:
- ARM64 has a dedicated zero register, so does not need to be
materialized.
- Byteswapping zero is still zero, so we can skip this step.
We could skip byteswapping for other values by immediately materializing
the byteswapped value in a register, but the benefits are not so clear
there (if the value needs to be materialized anyway, it is better to do
it up front).
Before:
0x5280001b mov w27, #0x0 ; =0
0xb9404fba ldr w26, [x29, #0x4c]
0x12881862 mov w2, #-0x40c4 ; =-16580
0x0b020342 add w2, w26, w2
0x5ac00b61 rev w1, w27
0xb8226b81 str w1, [x28, x2]
After:
0xb9404fbb ldr w27, [x29, #0x4c]
0x12881862 mov w2, #-0x40c4 ; =-16580
0x0b020362 add w2, w27, w2
0xb8226b9f str wzr, [x28, x2]
MUL and SUB can be combined in one instruction.
Before:
0x1b1a7c01 mul w1, w0, w26
0x4b010318 sub w24, w24, w1
After:
0x1b1ae018 msub w24, w0, w26, w24
No need to materialize the immediate if it is zero, we can just use WZR.
Before:
mov w27, #0x0 ; =0
str w27, [x29, #0x1178]
After:
str wzr, [x29, #0x1178]
When the immediate value is zero, we can do a negation. On ARM64 the NEG
/NEGS instructions are just an alias for SUB/SUBS with a hardcoded WZR.
Before:
```
ldr w22, [x29, #0x28]
mov w21, #0x0 ; =0
subs w22, w21, w22
```
After:
```
ldr w22, [x29, #0x28]
negs w22, w22
```
Sintendo